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1. 发明授权

US07201326B2 Information processing device 有权
标题翻译：信息处理装置
公开(公告)号：US07201326B2
公开(公告)日：2007-04-10
申请号：US10745540
申请日：2003-12-29
申请人： Takashi Endo , Masahiro Kaminaga , Takashi Watanabe , Kunihiko Nakada , Takashi Tsukamoto
发明人： Takashi Endo , Masahiro Kaminaga , Takashi Watanabe , Kunihiko Nakada , Takashi Tsukamoto
IPC分类号： G06K19/06
CPC分类号： G06F7/501 , G06F7/48 , G06F21/72 , G06F21/755 , G06F2207/7219 , H04L9/002 , H04L9/0861 , H04L9/0894
摘要： An object of the present invention is to prevent secret information that is being internally processed from being inferred through operational information of a secured device, including the current consumption information. One solution is provided by an information processing device having at least a key generation apparatus that generates key data automatically, an encryption unit that encrypts data with the corresponding key data, a register that stores a plurality of encrypted data items with the corresponding encryption key data items, and an arithmetic unit that performs operations using data expressed with the corresponding encryption key data and new key data as the input, encrypts the operation result with new input key data, and outputs the result, thereby being capable of performing internal processing on an encrypted data expression. Accordingly, only encrypted data is transferred on the internal or external data bus line.
摘要翻译：本发明的目的是通过包括当前消费信息的安全设备的操作信息来防止内部处理的秘密信息被推断。一种解决方案由至少具有自动生成密钥数据的密钥生成装置的信息处理装置提供，使用相应的密钥数据对数据进行加密的加密单元，存储多个加密的数据项与相应的加密密钥数据的寄存器项目，以及使用由对应的加密密钥数据和新密钥数据表示的数据作为输入进行操作的算术单元，用新的输入密钥数据对运算结果进行加密，并输出结果，从而能够对加密数据表达式。因此，仅在内部或外部数据总线上传送加密数据。

2. 发明授权

US06691921B2 Information processing device 有权
标题翻译：信息处理装置
公开(公告)号：US06691921B2
公开(公告)日：2004-02-17
申请号：US10217565
申请日：2002-08-14
申请人： Takashi Endo , Masahiro Kaminaga , Takashi Watanabe , Kunihiko Nakada , Takashi Tsukamoto
发明人： Takashi Endo , Masahiro Kaminaga , Takashi Watanabe , Kunihiko Nakada , Takashi Tsukamoto
IPC分类号： G06K1906
CPC分类号： G06F7/501 , G06F7/48 , G06F21/72 , G06F21/755 , G06F2207/7219 , H04L9/002 , H04L9/0861 , H04L9/0894
摘要： An object of the present invention is to prevent secret information that is being internally processed from being inferred through operational information of a secured device, including the current consumption information. One solution is provided by an information processing device having at least a key generation apparatus that generates key data automatically, an encryption unit that encrypts data with the corresponding key data, a register that stores a plurality of encrypted data items with the corresponding encryption key data items, and an arithmetic unit that performs operations using data expressed with the corresponding encryption key data and new key data as the input, encrypts the operation result with new input key data, and outputs the result, thereby being capable of performing internal processing on an encrypted data expression. Accordingly, only encrypted data is transferred on the internal or external data bus line.
摘要翻译：本发明的目的是通过包括当前消费信息的安全设备的操作信息来防止内部处理的秘密信息被推断。一种解决方案由至少具有自动生成密钥数据的密钥生成装置的信息处理装置提供，使用相应的密钥数据对数据进行加密的加密单元，存储多个加密的数据项与相应的加密密钥数据的寄存器项目，以及使用由对应的加密密钥数据和新密钥数据表示的数据作为输入进行操作的算术单元，用新的输入密钥数据对运算结果进行加密，并输出结果，从而能够对加密数据表达式。因此，仅在内部或外部数据总线上传送加密数据。

3. 发明授权

US07086087B1 Information processing device, card device and information processing system 失效
标题翻译：信息处理设备，卡设备和信息处理系统
公开(公告)号：US07086087B1
公开(公告)日：2006-08-01
申请号：US09599005
申请日：2000-06-22
申请人： Masahiro Kaminaga , Takashi Endo , Masaru Ohki , Takashi Tsukamoto , Hiroshi Watase , Chiaki Terauchi , Kunihiko Nakada , Nobutaka Nagasaki , Satoshi Taira , Yuuichirou Nariyoshi , Yasuko Fukuzawa
发明人： Masahiro Kaminaga , Takashi Endo , Masaru Ohki , Takashi Tsukamoto , Hiroshi Watase , Chiaki Terauchi , Kunihiko Nakada , Nobutaka Nagasaki , Satoshi Taira , Yuuichirou Nariyoshi , Yasuko Fukuzawa
IPC分类号： H04L9/00 , H04N7/167
CPC分类号： G07F7/1008 , G06K19/063 , G06Q20/341 , G07F7/082
摘要： It is a technological object of the present invention to provide an information processing device, a card and a card system that have a high level of security. In order to achieve the object described above, the present invention provides a data processing apparatus comprising at least a first information processing device and a second information processing device connected to the first information processing device by a signal line, the data processing apparatus having a means for changing power consumption on the signal line during transmission of a signal through the signal line in accordance with an actual state of the power consumption that would be observed when the means were not used. Furthermore, the present invention also provides another data processing apparatus comprising at least a first information processing device and a second information processing device connected to the first information processing device by a signal line wherein, between at least either the first information processing device or the second information processing device and the signal line, a signal from the first information processing device or the second information processing device can be encrypted and a signal received from the signal line can be decrypted. In addition, the present invention also provides a further data processing apparatus comprising at least an information processing device, an information memory device and a signal line connected at least to the information processing device wherein at least in an operation to store information into the information memory device, the information is encrypted, and information stored in the information memory device can be decrypted.
摘要翻译：本发明的技术目的在于提供具有高安全性的信息处理装置，卡片和卡片系统。为了实现上述目的，本发明提供了一种数据处理装置，包括至少第一信息处理装置和通过信号线连接到第一信息处理装置的第二信息处理装置，该数据处理装置具有装置用于根据当不使用装置时将观察到的功耗的实际状态，在通过信号线的信号传输期间改变信号线上的功率消耗。此外，本发明还提供了另一种数据处理装置，其至少包括通过信号线连接到第一信息处理装置的第一信息处理装置和第二信息处理装置，其中，在至少第一信息处理装置或第二信息处理装置信息处理装置和信号线，可以加密来自第一信息处理装置或第二信息处理装置的信号，并且可以解密从信号线接收的信号。另外，本发明还提供了一种数据处理装置，至少包括信息处理装置，信息存储装置和至少连接到信息处理装置的信号线，其中至少在将信息存储到信息存储器中的操作中信息被加密，并且存储在信息存储装置中的信息可被解密。

4. 发明授权

US07451485B2 Information processing unit having tamper-resistant system 有权
标题翻译：信息处理单元具有防篡改系统
公开(公告)号：US07451485B2
公开(公告)日：2008-11-11
申请号：US10124576
申请日：2002-04-18
申请人： Takashi Watanabe , Takashi Endo , Masahiro Kaminaga , Kunihiko Nakada , Yuuichirou Nariyoshi , Chiaki Tanimoto
发明人： Takashi Watanabe , Takashi Endo , Masahiro Kaminaga , Kunihiko Nakada , Yuuichirou Nariyoshi , Chiaki Tanimoto
IPC分类号： G06F9/00 , G06F11/00
CPC分类号： G06F21/52 , G06F21/556
摘要： A malfunction detection system is provided that can continue or terminate processing appropriately even if a malfunction occurs in an information processing unit. In this regard, the information processing unit receives branch direction information, carries out a conditional branch depending on the branch direction information, and performs an applicable operation on data I. At this time, the information processing unit performs an applicable operation on data J, other than the operated data I, in the conditional branch path and outputs the result for examination, thereby enabling validation of the conditional branch.
摘要翻译：提供了即使在信息处理单元中发生故障也可以适当地继续或终止处理的故障检测系统。在这方面，信息处理单元接收分支方向信息，根据分支方向信息执行条件分支，并且对数据I执行适用的操作。此时，信息处理单元对数据J执行适用的操作，在条件分支路径中除了操作数据I之外，并输出结果进行检查，从而能够验证条件分支。

5. 发明授权

US06907526B2 IC card and microprocessor 有权
标题翻译： IC卡和微处理器
公开(公告)号：US06907526B2
公开(公告)日：2005-06-14
申请号：US09754190
申请日：2001-01-05
申请人： Chiaki Tanimoto , Kunihiko Nakada , Takashi Tsukamoto , Shigeo Hirabayashi , Hiroshi Watase , Masatoshi Takahashi , Yuuichirou Nariyoshi
发明人： Chiaki Tanimoto , Kunihiko Nakada , Takashi Tsukamoto , Shigeo Hirabayashi , Hiroshi Watase , Masatoshi Takahashi , Yuuichirou Nariyoshi
IPC分类号： G06K19/07 , G06F9/38 , G06F21/00 , G06K19/073 , H04L9/00
CPC分类号： G06F21/77 , G06F9/3879 , G06F21/71 , G06F21/755 , G06F2207/7219 , G06K19/07363
摘要： Disclosed herein are an IC card and a microcomputer which have implemented the strengthening of security and the speeding up and enhancement of signal processing for the security. In an IC card, which is supplied with an operating voltage by an electrical connection between each of external terminals and a read/write device, and includes an input-output operation of data with an encoding process or a decoding process, a disturbance-aimed processing operation is included in the encoding process or decoding process to uniformalize timings provided to operate an internal circuit and its operating current. In a microcomputer having a module configuration including an input-output operation of data with an encoding process or a decoding process, a disturbance-aimed processing operation is included in the encoding process or decoding process to uniformalize timings provided to operate an internal circuit and its operating current.
摘要翻译：这里公开了实现了安全性的加强和信号处理的加速和增强的IC卡和微计算机。在通过每个外部端子和读/写装置之间的电连接提供工作电压的IC卡中，包括具有编码处理或解码处理的数据的输入输出操作，扰动目标处理操作被包括在编码处理或解码过程中，以使为操作内部电路提供的定时和其工作电流均匀化。在具有包括具有编码处理或解码处理的数据的输入输出操作的模块配置的微型计算机中，在编码处理或解码处理中包括干扰目标处理操作，以使为操作内部电路提供的定时被均匀化，工作电流。

6. 发明授权

US5581698A Semiconductor integrated circuit device with test mode for testing CPU using external Signal 失效
标题翻译：具有测试模式的半导体集成电路器件，用于使用外部信号测试CPU
公开(公告)号：US5581698A
公开(公告)日：1996-12-03
申请号：US048394
申请日：1993-04-15
申请人： Yoshiyuki Miwa , Tsuyoshi Jouno , Haruo Keida , Kunihiko Nakada , Hajime Yasuda
发明人： Yoshiyuki Miwa , Tsuyoshi Jouno , Haruo Keida , Kunihiko Nakada , Hajime Yasuda
IPC分类号： G01R31/3185 , G06F11/267 , G06F11/22 , G06F11/28
CPC分类号： G06F11/2236 , G01R31/318505
摘要： An output gate means is provided which is capable of outputting individual signals selectively to an internal bus; the individual signals are interchanged among a plurality of functional modules connected to the internal bus which is interfaced with an external circuit. An input gate means is provided which is capable of supplying selectively a signal, input to the internal bus, to a specified functional module in place of an individual signal.
摘要翻译：提供输出门装置，其能够将选择性地将各个信号输出到内部总线; 各个信号在连接到与外部电路接口的内部总线的多个功能模块中互换。提供了输入门装置，其能够选择性地向代表各个信号的指定功能模块提供输入到内部总线的信号。

7. 发明授权

US5005121A Integrated CPU and DMA with shared executing unit 失效
标题翻译：具有共享执行单元的集成CPU和DMA
公开(公告)号：US5005121A
公开(公告)日：1991-04-02
申请号：US326472
申请日：1989-03-20
申请人： Kunihiko Nakada , Yasushi Akao
发明人： Kunihiko Nakada , Yasushi Akao
IPC分类号： G06F9/26 , G06F9/22 , G06F13/10 , G06F13/28 , G06F15/78
CPC分类号： G06F13/285
摘要： A data processor controller for a microprogramming system is constructed with a single operation execution unit serving both a microprocessor and a peripheral device such as a direct memory access controller. In addition to the single operation execution unit, the controller includes a micro-memory which stores micro-instructions for controlling both the microprocessor and the peripheral device, and address registers, multiplexers and decoders integrated into a single device. Different ROM address registers in the controller are separately assigned to provide an address decoder with addresses of selected memory locations in the micro-memory containing the micro-instructions for the microprocessor and the peripheral device, thereby enabling the controller, through multiplexing between the address registers, to use the arithmetic execution unit, counter and bus interface of the single operation exeuction unit on a time sharing basis, for controlling the functions of both the microprocessor and the peripheral device.
摘要翻译：用于微程序系统的数据处理器控制器由单个操作执行单元构成，该单个操作执行单元用于微处理器和诸如直接存储器访问控制器的外围设备。除了单个操作执行单元之外，控制器还包括微存储器，其存储用于控制微处理器和外围设备的微指令，以及集成到单个设备中的地址寄存器，复用器和解码器。控制器中的不同的ROM地址寄存器被分别分配给地址解码器，该地址解码器具有包含微处理器和外围设备的微指令的微存储器中所选择的存储器位置的地址，从而使控制器能够通过地址寄存器在时间分配的基础上使用单个操作单元的算术执行单元，计数器和总线接口，用于控制微处理器和外围设备的功能。

8. 发明授权

US5226173A Integrated data processor having mode control register for controlling operation mode of serial communication unit 失效
标题翻译：具有用于控制串行通信单元的操作模式的模式控制寄存器的集成数据处理器
公开(公告)号：US5226173A
公开(公告)日：1993-07-06
申请号：US850856
申请日：1992-03-13
申请人： Hisao Sasaki , Takeshi Miyazaki , Shiro Baba , Kunihiko Nakada , Yasushi Akao
发明人： Hisao Sasaki , Takeshi Miyazaki , Shiro Baba , Kunihiko Nakada , Yasushi Akao
IPC分类号： G06F13/38
CPC分类号： G06F13/385
摘要： A reception unit for providing data supplied from a serial input circuit to an inner bus and a transmission unit for providing the data supplied from the inner bus to a serial output circuit hold at least two types of control procedures selected from HDLC procedure, BI-SYNC procedure and start-stop synchronous procedure as control procedures for data transmission/reception, and the control procedures held by these units can be selected alternatively based on a mode control data written in a mode control register by a processor.
摘要翻译：用于将从串行输入电路提供的数据提供给内部总线的接收单元和用于将从内部总线提供的数据提供给串行输出电路的传输单元保持从HDLC程序，BI-SYNC中选择的至少两种类型的控制程序作为用于数据发送/接收的控制过程的程序和起始 - 停止同步过程，并且可以基于由处理器写入模式控制寄存器的模式控制数据来替代地选择由这些单元保持的控制过程。

9. 发明授权

US07379967B2 Download method for file by bit torrent protocol 失效
标题翻译：下载方式的文件按位洪流协议
公开(公告)号：US07379967B2
公开(公告)日：2008-05-27
申请号：US10546297
申请日：2005-01-28
申请人： Masahiro Izutsu , Kunihiko Nakada , Michimasa Suzawa
发明人： Masahiro Izutsu , Kunihiko Nakada , Michimasa Suzawa
IPC分类号： G06F15/16
CPC分类号： H04L67/06 , H04L67/104 , H04L67/1063 , H04L67/1076 , H04L67/1091
摘要： The present invention relates to the improvement of the Bit Torrent protocol, which is one of the P2P protocols. A seeder flag is added to the active peer table. First a super seeder having the original is activated, and the super seeder is stopped when the total value of the seeder flags (number of activated seeders) reaches a certain level. The super seeders are activated only when the seeders having the original of a file are insufficient on the network, and are stopped when excessive. By this dynamic control, the number of activated processes of the super seeders can be decreased.
摘要翻译：本发明涉及P2P协议之一的Bit Torrent协议的改进。播放器标志被添加到活动对等体表。首先，激活原始的超级播种机，当播种机标志的总数（已激活播种机的数量）达到一定水平时，超级播种机停止。超级播种机仅在具有文件原件的播种机在网络上不足时被激活，并且在过量时停止。通过这种动态控制，可以减少超级播种机的激活过程的数量。

10. 发明授权

US5228139A Semiconductor integrated circuit device with test mode for testing CPU using external signal 失效
标题翻译：具有测试模式的半导体集成电路器件，用于使用外部信号测试CPU
公开(公告)号：US5228139A
公开(公告)日：1993-07-13
申请号：US840633
申请日：1992-02-21
申请人： Yoshiyuki Miwa , Tsuyoshi Jouno , Haruo Keida , Kunihiko Nakada , Hajime Yasuda
发明人： Yoshiyuki Miwa , Tsuyoshi Jouno , Haruo Keida , Kunihiko Nakada , Hajime Yasuda
IPC分类号： G01R31/3185 , G06F11/267
CPC分类号： G06F11/2236 , G01R31/318505
摘要： An output gate means is provided which is capable of outputting individual signals selectively to an internal bus; the individual signals are interchanged among a plurality of functional modules connected to the internal bus which is interfaced with an external circuit. An input gate means is provided which is capable of supplying selectively a signal, input to the internal bus, to a specified functional module in place of an individual signal.
摘要翻译：提供输出门装置，其能够将选择性地将各个信号输出到内部总线; 各个信号在连接到与外部电路接口的内部总线的多个功能模块中互换。提供了输入门装置，其能够选择性地向代表各个信号的指定功能模块提供输入到内部总线的信号。

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