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1. 发明授权

US5361374A Integrated data processor having mode control register for controlling operation mode of serial communication unit 失效
标题翻译：具有用于控制串行通信单元的操作模式的模式控制寄存器的集成数据处理器
公开(公告)号：US5361374A
公开(公告)日：1994-11-01
申请号：US49347
申请日：1993-04-21
申请人： Hisao Sasaki , Takeshi Miyazaki , Shiro Baba , Kunihiko Nakada , Yasushi Akao
发明人： Hisao Sasaki , Takeshi Miyazaki , Shiro Baba , Kunihiko Nakada , Yasushi Akao
IPC分类号： G06F13/38 , G06F13/00
CPC分类号： G06F13/385
摘要： A reception unit for providing data supplied from a serial input circuit to an inner bus and a transmission unit for providing the data supplied from the inner bus to a serial output circuit hold at least two sorts of control procedures among HDLC procedure, BI-SYNC procedure and start-stop synchronous procedure as control procedures for data transmission/reception, and the control procedures held by these units can be selected alternatively based on a command of the processor.
摘要翻译：用于将从串行输入电路提供的数据提供给内部总线的接收单元和用于将从内部总线提供的数据提供给串行输出电路的传输单元在HDLC程序，BI-SYNC程序中保持至少两种控制程序以及作为数据发送/接收的控制过程的起始 - 停止同步过程，并且可以基于处理器的命令交替地选择由这些单元保持的控制过程。

2. 发明授权

US5005121A Integrated CPU and DMA with shared executing unit 失效
标题翻译：具有共享执行单元的集成CPU和DMA
公开(公告)号：US5005121A
公开(公告)日：1991-04-02
申请号：US326472
申请日：1989-03-20
申请人： Kunihiko Nakada , Yasushi Akao
发明人： Kunihiko Nakada , Yasushi Akao
IPC分类号： G06F9/26 , G06F9/22 , G06F13/10 , G06F13/28 , G06F15/78
CPC分类号： G06F13/285
摘要： A data processor controller for a microprogramming system is constructed with a single operation execution unit serving both a microprocessor and a peripheral device such as a direct memory access controller. In addition to the single operation execution unit, the controller includes a micro-memory which stores micro-instructions for controlling both the microprocessor and the peripheral device, and address registers, multiplexers and decoders integrated into a single device. Different ROM address registers in the controller are separately assigned to provide an address decoder with addresses of selected memory locations in the micro-memory containing the micro-instructions for the microprocessor and the peripheral device, thereby enabling the controller, through multiplexing between the address registers, to use the arithmetic execution unit, counter and bus interface of the single operation exeuction unit on a time sharing basis, for controlling the functions of both the microprocessor and the peripheral device.
摘要翻译：用于微程序系统的数据处理器控制器由单个操作执行单元构成，该单个操作执行单元用于微处理器和诸如直接存储器访问控制器的外围设备。除了单个操作执行单元之外，控制器还包括微存储器，其存储用于控制微处理器和外围设备的微指令，以及集成到单个设备中的地址寄存器，复用器和解码器。控制器中的不同的ROM地址寄存器被分别分配给地址解码器，该地址解码器具有包含微处理器和外围设备的微指令的微存储器中所选择的存储器位置的地址，从而使控制器能够通过地址寄存器在时间分配的基础上使用单个操作单元的算术执行单元，计数器和总线接口，用于控制微处理器和外围设备的功能。

3. 发明授权

US5226173A Integrated data processor having mode control register for controlling operation mode of serial communication unit 失效
标题翻译：具有用于控制串行通信单元的操作模式的模式控制寄存器的集成数据处理器
公开(公告)号：US5226173A
公开(公告)日：1993-07-06
申请号：US850856
申请日：1992-03-13
申请人： Hisao Sasaki , Takeshi Miyazaki , Shiro Baba , Kunihiko Nakada , Yasushi Akao
发明人： Hisao Sasaki , Takeshi Miyazaki , Shiro Baba , Kunihiko Nakada , Yasushi Akao
IPC分类号： G06F13/38
CPC分类号： G06F13/385
摘要： A reception unit for providing data supplied from a serial input circuit to an inner bus and a transmission unit for providing the data supplied from the inner bus to a serial output circuit hold at least two types of control procedures selected from HDLC procedure, BI-SYNC procedure and start-stop synchronous procedure as control procedures for data transmission/reception, and the control procedures held by these units can be selected alternatively based on a mode control data written in a mode control register by a processor.
摘要翻译：用于将从串行输入电路提供的数据提供给内部总线的接收单元和用于将从内部总线提供的数据提供给串行输出电路的传输单元保持从HDLC程序，BI-SYNC中选择的至少两种类型的控制程序作为用于数据发送/接收的控制过程的程序和起始 - 停止同步过程，并且可以基于由处理器写入模式控制寄存器的模式控制数据来替代地选择由这些单元保持的控制过程。

4. 发明授权

US07069423B2 Microcomputer 失效
公开(公告)号：US07069423B2
公开(公告)日：2006-06-27
申请号：US10201402
申请日：2002-07-22
申请人： Hiroshi Ohsuga , Atsushi Kiuchi , Hironobu Hasegawa , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
发明人： Hiroshi Ohsuga , Atsushi Kiuchi , Hironobu Hasegawa , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
IPC分类号： G06F9/30
CPC分类号： G06F9/3893 , G06F9/3001 , G06F9/30043 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/3017 , G06F9/345 , G06F9/3552 , G06F9/3802 , G06F9/3814 , G06F9/3824 , G06F9/3877 , G06F15/7817
摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

5. 发明申请

US20050251651A1 Microcomputer and dividing circuit 审中-公开
标题翻译：微电脑和分频电路
公开(公告)号：US20050251651A1
公开(公告)日：2005-11-10
申请号：US11120105
申请日：2005-05-03
申请人： Shumpei Kawasaki , Eiji Sakakibara , Kaoru Fukada , Takanaga Yamazaki , Yasushi Akao , Shiro Baba , Toshimasa Kihara , Keiichi Kurakazu , Takashi Tsukamoto , Shigeki Masumura , Yasuhiro Tawara , Yugo Kashiwagi , Shuya Fujita , Katsuhiko Ishida , Noriko Sawa , Yoichi Asano , Hideaki Chaki , Tadahiko Sugawara , Masahiro Kainaga , Kouki Noguchi , Mitsuru Watabe
发明人： Shumpei Kawasaki , Eiji Sakakibara , Kaoru Fukada , Takanaga Yamazaki , Yasushi Akao , Shiro Baba , Toshimasa Kihara , Keiichi Kurakazu , Takashi Tsukamoto , Shigeki Masumura , Yasuhiro Tawara , Yugo Kashiwagi , Shuya Fujita , Katsuhiko Ishida , Noriko Sawa , Yoichi Asano , Hideaki Chaki , Tadahiko Sugawara , Masahiro Kainaga , Kouki Noguchi , Mitsuru Watabe
IPC分类号： G06F9/28 , G06F7/483 , G06F7/52 , G06F7/527 , G06F7/535 , G06F7/537 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/318 , G06F9/32 , G06F9/38
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.
摘要翻译：这里公开了采用通用寄存器方法的微计算机MCU。微型计算机能够使用效率低且系统成本低的程序容量小或高程序存储器，同时具有简化指令解码的优点，如具有现有技术的固定长度指令格式的RISC机器，通过采用固定长度指令格式，其具有功率2但是比馈送到指令执行装置的最大数据字长度的位数更小的位数。并且，通过注意码位来执行编码除法的控制。

6. 发明授权

US06735683B2 Single-chip microcomputer with hierarchical internal bus structure having data and address signal lines coupling CPU with other processing elements 失效
标题翻译：具有分层内部总线结构的单片机具有将CPU与其他处理元件耦合的数据和地址信号线
公开(公告)号：US06735683B2
公开(公告)日：2004-05-11
申请号：US10264618
申请日：2002-10-04
申请人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
发明人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
IPC分类号： G06F1500
CPC分类号： H04W52/0229 , G06F15/7814 , Y02D10/12 , Y02D10/13 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译：一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线，其具有与其连接的周边模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。此外，隔离所需要的没有操作速度的外围模块，从而可以降低功耗。

7. 发明授权

US6002856A Semiconductor integrated circuit device 失效
公开(公告)号：US6002856A
公开(公告)日：1999-12-14
申请号：US203618
申请日：1998-12-01
申请人： Yasushi Akao , Kenichi Kuroda
发明人： Yasushi Akao , Kenichi Kuroda
IPC分类号： G06F15/78 , G06F17/60
CPC分类号： G06F15/7814
摘要： A semiconductor integrated circuit device comprising a one-chip microcomputer having a nonvolatile memory circuit to and from which write and read operations are carried out at high speed in keeping with the cycle time of the processor. Part of the memory circuit is set aside as a read-only area for accommodating a data processing program, and the rest of the memory is used to write and read data thereto and therefrom. With no need to optimize the assignments of the ROM and RAM parts in the memory circuit, the one-chip microchip is easy to design and manufacture with high productivity. With the program storage area established as desired, users enjoy more convenience use of the one-chip microcomputer than before.

8. 发明授权

US5682545A Microcomputer having 16 bit fixed length instruction format 失效
标题翻译：微电脑具有16位固定长度指令格式
公开(公告)号：US5682545A
公开(公告)日：1997-10-28
申请号：US475459
申请日：1995-06-07
申请人： Shumpei Kawasaki , Eiji Sakakibara , Kaoru Fukada , Takanaga Yamazaki , Yasushi Akao , Shiro Baba , Toshimasa Kihara , Keiichi Kurakazu , Takashi Tsukamoto , Shigeki Masumura , Yasuhiro Tawara , Yugo Kashiwagi , Shuya Fujita , Katsuhiko Ishida , Noriko Sawa , Yoichi Asano , Hideaki Chaki , Tadahiko Sugawara , Masahiro Kainaga , Kouki Noguchi , Mitsuru Watabe
发明人： Shumpei Kawasaki , Eiji Sakakibara , Kaoru Fukada , Takanaga Yamazaki , Yasushi Akao , Shiro Baba , Toshimasa Kihara , Keiichi Kurakazu , Takashi Tsukamoto , Shigeki Masumura , Yasuhiro Tawara , Yugo Kashiwagi , Shuya Fujita , Katsuhiko Ishida , Noriko Sawa , Yoichi Asano , Hideaki Chaki , Tadahiko Sugawara , Masahiro Kainaga , Kouki Noguchi , Mitsuru Watabe
IPC分类号： G06F9/28 , G06F7/483 , G06F7/52 , G06F7/527 , G06F7/535 , G06F7/537 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/318 , G06F9/32 , G06F9/38 , G01F15/00
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.
摘要翻译：这里公开了采用通用寄存器方法的微计算机MCU。微型计算机能够使用效率低且系统成本低的程序容量小或高程序存储器，同时具有简化指令解码的优点，如具有现有技术的固定长度指令格式的RISC机器，通过采用固定长度指令格式，其具有功率2但是比馈送到指令执行装置的最大数据字长度的位数更小的位数。并且，通过注意码位来执行编码除法的控制。

9. 发明授权

US5307464A Microprocessor and method for setting up its peripheral functions 失效
标题翻译：微处理器和设置其外设功能的方法
公开(公告)号：US5307464A
公开(公告)日：1994-04-26
申请号：US621641
申请日：1990-12-03
申请人： Yasushi Akao , Shiro Baba , Yoshiyuki Miwa , Terumi Sawase , Yuji Sato , Shigeki Masumura
发明人： Yasushi Akao , Shiro Baba , Yoshiyuki Miwa , Terumi Sawase , Yuji Sato , Shigeki Masumura
IPC分类号： G06F13/12 , G06F15/78 , G06F13/00
CPC分类号： G06F13/124 , G06F15/7814
摘要： A single chip microprocessor 1 includes a CPU 2 and a sub-processor 5 for software implementation of peripheral functions of the microprocessor 1. Sub-processor 5 includes electrically writable internal storage devices microprogram memory unit 13 and sequence control memory unit 62 for storing the software. Peripheral functions are defined and/or modified by writing software into the memory units 13 and 62. Accordingly, the time it takes to define and/or modify the peripheral functions is the time it takes to program the memory units 13 and 62. The sub-processor 5 also includes an execution unit 16 for executing a plurality of tasks and an address control circuit 14 for providing addresses to the microprogram memory unit 13. Additionally, the microprogram memory unit 13 provides microinstructions to the execution unit 16. The sequence control memory unit 62 is part of the address control circuit 14 which also includes a plurality of address registers MAR0 to MAR11. The sequence control memory unit 62 is used for storing information regarding the order of selection of the multiple address registers MAR0 to MAR11. One of the address registers MAR0 to MAR11 is selected each time the sequence control memory unit 62 is read. A microaddress stored in the selected address register is then supplied to the microprogram memory unit 13.
摘要翻译：单片微处理器1包括用于软件实现微处理器1的外围功能的CPU 2和子处理器5.子处理器5包括电可写内部存储设备微程序存储单元13和用于存储软件的顺控控制存储单元62 。通过将软件写入存储器单元13和62来定义和/或修改外围功能。因此，定义和/或修改外围功能所花费的时间是编程存储器单元13和62所花费的时间。子处理器5还包括用于执行多个任务的执行单元16和用于向微程序存储单元13提供地址的地址控制电路14.另外，微程序存储单元13向执行单元16提供微指令。顺序控制存储器单元62是还包括多个地址寄存器MAR0至MAR11的地址控制电路14的一部分。顺序控制存储器单元62用于存储关于多个地址寄存器MAR0至MAR11的选择顺序的信息。每次读序列控制存储器单元62选择地址寄存器MAR0至MAR11中的一个。存储在选择的地址寄存器中的微地址然后被提供给微程序存储单元13。

10. 发明申请

US20120023281A1 Single-chip microcomputer 审中-公开
标题翻译：单片机
公开(公告)号：US20120023281A1
公开(公告)日：2012-01-26
申请号：US13065588
申请日：2011-03-24
申请人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
发明人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
IPC分类号： G06F13/36 , G11C11/34
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译：一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线，其具有与其连接的周边模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。此外，隔离所需要的没有操作速度的外围模块，从而可以降低功耗。

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