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1. 发明授权

US07763500B2 Method for manufacturing semiconductor storage device comprising a slow cooling step 失效
标题翻译：一种制造半导体存储装置的方法，包括缓慢冷却步骤
公开(公告)号：US07763500B2
公开(公告)日：2010-07-27
申请号：US11498129
申请日：2006-08-03
申请人： Takashi Arao , Kenichi Koyanagi , Kenji Komeda , Naruhiko Nakanishi , Hideki Gomi
发明人： Takashi Arao , Kenichi Koyanagi , Kenji Komeda , Naruhiko Nakanishi , Hideki Gomi
IPC分类号： H01L21/335 , H01L21/8232
CPC分类号： H01L28/40 , H01L27/10852 , H01L28/84
摘要： First, a base structure provided with the main parts of a memory cell is prepared, and a lower electrode comprising a polycrystalline silicon film is thereafter formed on the base structure. Next, the surface of the lower electrode is thermally nitrided at a predetermined temperature to form a silicon nitride film. In the thermal nitridation of the lower electrode, the temperature is increased to a predetermined nitriding temperature, after which the temperature is reduced at a rate that is more gradual than usual. Aluminum oxide (Al2O3) or another metal oxide dielectric film is thereafter formed as the capacitive insulating film on the lower electrode, and an upper electrode is formed on the capacitive insulating film.
摘要翻译：首先，准备设置有存储单元的主要部分的基底结构，然后在基底结构上形成包括多晶硅膜的下部电极。接下来，将下电极的表面在预定温度下热氮化，以形成氮化硅膜。在下电极的热氮化中，将温度升高到预定的氮化温度，之后以比通常更渐进的速度降低温度。此后，在下电极上形成作为电容绝缘膜的氧化铝（Al2O3）或其他金属氧化物电介质膜，在电容绝缘膜上形成上电极。

2. 发明申请

US20070032034A1 Method for manufacturing semiconductor storage device 失效
标题翻译：半导体存储装置的制造方法
公开(公告)号：US20070032034A1
公开(公告)日：2007-02-08
申请号：US11498129
申请日：2006-08-03
申请人： Takashi Arao , Kenichi Koyanagi , Kenji Komeda , Naruhiko Nakanishi , Hideki Gomi
发明人： Takashi Arao , Kenichi Koyanagi , Kenji Komeda , Naruhiko Nakanishi , Hideki Gomi
IPC分类号： H01L21/20
CPC分类号： H01L28/40 , H01L27/10852 , H01L28/84
摘要： First, a base structure provided with the main parts of a memory cell is prepared, and a lower electrode comprising a polycrystalline silicon film is thereafter formed on the base structure. Next, the surface of the lower electrode is thermally nitrided at a predetermined temperature to form a silicon nitride film. In the thermal nitridation of the lower electrode, the temperature is increased to a predetermined nitriding temperature, after which the temperature is reduced at a rate that is more gradual than usual. Aluminum oxide (Al2O3) or another metal oxide dielectric film is thereafter formed as the capacitive insulating film on the lower electrode, and an upper electrode is formed on the capacitive insulating film.
摘要翻译：首先，准备设置有存储单元的主要部分的基底结构，然后在基底结构上形成包括多晶硅膜的下部电极。接下来，将下电极的表面在预定温度下热氮化，以形成氮化硅膜。在下电极的热氮化中，将温度升高到预定的氮化温度，之后以比通常更渐进的速度降低温度。然后在下电极上形成氧化铝（Al 2 O 3 3）或其它金属氧化物电介质膜作为电容绝缘膜，并且上电极形成在电容绝缘膜。

3. 发明授权

US07754563B2 Nanolaminate-structure dielectric film forming method 有权
标题翻译：纳米结构电介质膜形成方法
公开(公告)号：US07754563B2
公开(公告)日：2010-07-13
申请号：US11776300
申请日：2007-07-11
申请人： Naruhiko Nakanishi
发明人： Naruhiko Nakanishi
IPC分类号： H01L21/8242 , H01L21/44
CPC分类号： H01L28/40 , H01L21/02178 , H01L21/02197 , H01L21/0228 , H01L21/3142 , H01L21/31604 , H01L21/3162 , H01L21/31691 , H01L27/10852
摘要： Nanolaminate-structure SrO/TiO films are formed on a lower electrode of a capacitor by molecular layer deposition kept in a rate-determined state by a surface reaction. The nanolaminate-structure SrO/TiO films are formed by alternately laminating one or more and 20 or less SrO molecular layers and one or more and 20 or less TiO molecular layers at 150° C. or more and 400° C. or less and at 10 Torr or more and the atmospheric pressure or less. This makes it possible to obtain the nanolaminate-structure SrO/TiO films with a high permittivity and a high coverage and with no occurrence of crystalline foreign substance.
摘要翻译：通过表面反应保持在速率确定状态的分子层沉积，在电容器的下电极上形成纳米层状结构的SrO / TiO膜。纳米级结构的SrO / TiO薄膜是通过在150℃以上且400℃以下的交联层叠一个或多于20个或更少的SrO分子层和一个或多于20个或更少的TiO分子层而形成的。 10乇以上，大气压以下。这使得可以获得具有高介电常数和高覆盖率且不发生结晶异物的纳米级结构的SrO / TiO薄膜。

4. 发明授权

US06713343B2 Method of forming a semiconductor device with a capacitor including a polycrystalline tantalum oxide film dielectric 失效
标题翻译：用包括多晶氧化钽膜电介质的电容器形成半导体器件的方法
公开(公告)号：US06713343B2
公开(公告)日：2004-03-30
申请号：US10388618
申请日：2003-03-17
申请人： Yasuhiro Sugawara , Shinpei Iijima , Yuzuru Oji , Naruhiko Nakanishi , Misuzu Kanai , Masahiko Hiratani
发明人： Yasuhiro Sugawara , Shinpei Iijima , Yuzuru Oji , Naruhiko Nakanishi , Misuzu Kanai , Masahiko Hiratani
IPC分类号： H01L218242
CPC分类号： H01L27/1085 , H01L21/02183 , H01L21/02271 , H01L21/02304 , H01L21/02337 , H01L21/02356 , H01L21/31604 , H01L27/10814 , H01L27/10817 , H01L27/10852 , H01L27/10876 , H01L27/10891 , H01L27/10894 , H01L28/40
摘要： An integrated semiconductor device has an improved reliability and is adapted to a higher degree of integration without reducing the accumulated electric charge of each information storage capacity element. The semiconductor device is provided with a DRAM having memory cells, each comprising an information storage capacity element C connected in series to a memory cell selection MISFET Qs formed on a main surface of a semiconductor substrate 1 and having a lower electrode 54, a capacity insulating film 58 and an upper electrode 59. The lower electrode 54 is made of ruthenium film oriented in a particular plane bearing, e.g., a (002) plane, and the capacity insulating film 58 is made of a polycrystalline tantalum film obtained by thermally treating an amorphous tantalum oxide film containing crystal of tantalum oxide in an as-deposited state for crystallization.
摘要翻译：集成半导体器件具有改进的可靠性并且适于更高的集成度，而不减少每个信息存储电容元件的累积电荷。半导体器件具有DRAM，其具有存储单元，每个DRAM包括与形成在半导体衬底1的主表面上的存储单元选择MISFET Qs串联连接的信息存储电容元件C，具有下电极54，电容绝缘膜58和上电极59.下电极54由在特定平面轴承（例如（002））面取向的钌膜制成，并且电容绝缘膜58由通过热处理得到的多晶钽膜制成含有沉淀状态的结晶用氧化钽晶体的无定形氧化钽膜。

5. 发明授权

US07872294B2 Semiconductor device having a capacitance element and method of manufacturing the same 有权
标题翻译：具有电容元件的半导体器件及其制造方法
公开(公告)号：US07872294B2
公开(公告)日：2011-01-18
申请号：US12698417
申请日：2010-02-02
申请人： Naruhiko Nakanishi
发明人： Naruhiko Nakanishi
IPC分类号： H01L31/119 , H01L21/44
CPC分类号： H01L28/65 , H01L27/10814 , H01L27/10852
摘要： A dielectric film is formed by depositing an amorphous strontium oxide film to a thickness of one to several atomic layers on a first electrode layer, then depositing an amorphous titanium oxide film to a thickness of one to several atomic layers on the amorphous strontium oxide film, and then heat-treating a laminated film of the amorphous strontium oxide film and the amorphous titanium oxide film at a temperature close to a crystallization start temperature, thereby converting the laminated film to a single-layer amorphous strontium titanate film containing a plurality of crystal grains therein. The laminated film may have a plurality of amorphous strontium oxide films and a plurality of amorphous titanium oxide films that are alternately laminated. A semiconductor device includes a capacitor having as its dielectric film a single-layer amorphous strontium titanate film containing a plurality of crystal grains therein.
摘要翻译：通过在第一电极层上沉积厚度为一至几个原子层的无定形氧化锶膜，然后在无定形氧化锶膜上沉积一至几个原子层的厚度的无定形氧化钛膜，形成电介质膜，然后在接近结晶开始温度的温度下对无定型氧化锶膜和非晶态氧化钛膜的层叠膜进行热处理，从而将层叠膜转化为含有多个晶粒的单层无定形钛酸锶膜其中。层叠膜可以具有交替层叠的多个无定形氧化锶膜和多个无定形氧化钛膜。半导体器件包括具有作为其电介质膜的电容器，其中含有多个晶粒的单层无定形钛酸锶膜。

6. 发明授权

US06583463B1 Semiconductor integrated circuit device with information storage capacitor having ruthenium dioxide lower electrode and crystallized TA2O5 capacitor insulator 失效
标题翻译：具有信息存储电容器的半导体集成电路器件具有二氧化钌下电极和结晶化的TA2O5电容绝缘体
公开(公告)号：US06583463B1
公开(公告)日：2003-06-24
申请号：US09172196
申请日：1998-10-14
申请人： Naruhiko Nakanishi , Nobuyoshi Kobayashi , Yuzuru Ohji , Sinpei Iijima , Yasuhiro Sugawara , Misuzu Kanai
发明人： Naruhiko Nakanishi , Nobuyoshi Kobayashi , Yuzuru Ohji , Sinpei Iijima , Yasuhiro Sugawara , Misuzu Kanai
IPC分类号： H01L27108
CPC分类号： H01L21/31604 , H01L21/02183 , H01L21/02271 , H01L21/02337 , H01L27/10814 , H01L27/10852 , H01L27/10882 , H01L27/10894 , H01L28/56 , H01L28/60 , H01L28/65
摘要： A semiconductor integrated circuit device including a memory cell comprising a memory cell selecting MISFET Qs formed on the main surface of a semiconductor substrate 1 and an information storage capacitor C that is connected in series to said memory cell selecting MISFET Qs, and that have a lower electrode 54, a capacitor insulator 58 and an upper electrode 59, wherein the lower electrode 54 is made of a conductive material containing ruthenium dioxide (RuO2) as principle ingredient and the capacitor insulator 58 is made of crystalline tantalum pentoxide. Thus, the capacitance required for the memory cells of a 256 Mbits DRAM or those of a DRAM of a later generation can be secured.
摘要翻译：一种半导体集成电路器件，包括存储单元，该存储单元包括形成在半导体衬底1的主表面上的存储单元选择MISFET Qs和与所述存储单元选择MISFET Qs串联连接的信息存储电容器C，电极54，电容器绝缘体58和上电极59，其中下电极54由含有二氧化钌（RuO 2）作为主要成分的导电材料制成，并且电容器绝缘体58由结晶的五氧化二钽制成。因此，可以确保256Mbits DRAM的存储单元或后一代的DRAM的存储单元所需的电容。

7. 发明授权

US07691743B2 Semiconductor device having a capacitance element and method of manufacturing the same 有权
标题翻译：具有电容元件的半导体器件及其制造方法
公开(公告)号：US07691743B2
公开(公告)日：2010-04-06
申请号：US11923062
申请日：2007-10-24
申请人： Naruhiko Nakanishi
发明人： Naruhiko Nakanishi
IPC分类号： H01L21/44 , H01L31/119
CPC分类号： H01L28/65 , H01L27/10814 , H01L27/10852
摘要： A dielectric film is formed by depositing an amorphous strontium oxide film to a thickness of one to several atomic layers on a first electrode layer, then depositing an amorphous titanium oxide film to a thickness of one to several atomic layers on the amorphous strontium oxide film, and then heat-treating a laminated film of the amorphous strontium oxide film and the amorphous titanium oxide film at a temperature close to a crystallization start temperature, thereby converting the laminated film to a single-layer amorphous strontium titanate film containing a plurality of crystal grains therein. The laminated film may have a plurality of amorphous strontium oxide films and a plurality of amorphous titanium oxide films that are alternately laminated. A semiconductor device includes a capacitor having as its dielectric film a single-layer amorphous strontium titanate film containing a plurality of crystal grains therein.
摘要翻译：通过在第一电极层上沉积厚度为一至几个原子层的无定形氧化锶膜，然后在无定形氧化锶膜上沉积一至几个原子层的厚度的无定形氧化钛膜，形成电介质膜，然后在接近结晶开始温度的温度下对无定型氧化锶膜和非晶态氧化钛膜的层叠膜进行热处理，从而将层叠膜转化为含有多个晶粒的单层无定形钛酸锶膜其中。层叠膜可以具有交替层叠的多个无定形氧化锶膜和多个无定形氧化钛膜。半导体器件包括具有作为其电介质膜的电容器，其中含有多个晶粒的单层无定形钛酸锶膜。

8. 发明申请

US20070077759A1 Method for forming dielectric film and method for manufacturing semiconductor device by using the same 审中-公开
标题翻译：电介质膜的形成方法及其制造方法
公开(公告)号：US20070077759A1
公开(公告)日：2007-04-05
申请号：US11542152
申请日：2006-10-04
申请人： Naruhiko Nakanishi
发明人： Naruhiko Nakanishi
IPC分类号： H01L21/44
CPC分类号： H01L21/3141 , H01L21/02178 , H01L21/0228 , H01L21/02304 , H01L21/31604 , H01L21/3162 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L28/40
摘要： In a method of manufacturing a semiconductor device, a lower electrode of a capacitor is formed above a semiconductor substrate. Thermal treatment is carried out to a base layer, which includes the lower electrode, in an atomic layer deposition apparatus. A dielectric film is formed on the base layer after the thermal treatment by an atomic layer deposition method without exposing the substrate to air. An upper electrode of the capacitor is formed on the dielectric film.
摘要翻译：在制造半导体器件的方法中，在半导体衬底之上形成电容器的下电极。在原子层沉积装置中对包括下电极的基层进行热处理。在通过原子层沉积方法进行热处理之后，在基底层上形成介电膜而不将基板暴露在空气中。在电介质膜上形成电容器的上电极。

9. 发明授权

US06664157B2 Semiconductor integrated circuit device and the method of producing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06664157B2
公开(公告)日：2003-12-16
申请号：US09775547
申请日：2001-02-05
申请人： Shinpei Iijima , Yoshitaka Nakamura , Masahiko Hiratani , Yuichi Matsui , Naruhiko Nakanishi
发明人： Shinpei Iijima , Yoshitaka Nakamura , Masahiko Hiratani , Yuichi Matsui , Naruhiko Nakanishi
IPC分类号： H01L218242
CPC分类号： H01L27/10855 , H01L27/10888 , H01L28/91
摘要： Plug electrodes of silicon are formed so as to be buried in through holes in a first insulating film, the plug electrodes being electrically connected to the source and drain regions of a MISFET on the main surface of a semiconductor substrate. Then, a second insulating film is deposited thereon and holes are formed therein such that the plug electrodes of silicon are exposed. A barrier film is formed on the surfaces of the silicon plugs, and in the holes a dielectric is formed to form lower electrodes of the capacitor elements and an upper electrode therefor.
摘要翻译：形成硅的插入电极以埋在第一绝缘膜的通孔中，插塞电极与半导体衬底的主表面上的MISFET的源极和漏极区域电连接。然后，在其上沉积第二绝缘膜，并在其中形成孔，使得硅的插塞电极露出。在硅插头的表面上形成阻挡膜，并且在孔中形成电介质以形成电容器元件的下电极和用于其的上电极。

10. 发明授权

US06627497B2 Semiconductor integrated circuit device and method of manufacturing the same 失效
公开(公告)号：US06627497B2
公开(公告)日：2003-09-30
申请号：US10162192
申请日：2002-06-05
申请人： Naruhiko Nakanishi , Nobuyoshi Kobayashi , Yuzuru Ohji , Sinpei Iijima , Yasuhiro Sugawara , Misuzu Kanai
发明人： Naruhiko Nakanishi , Nobuyoshi Kobayashi , Yuzuru Ohji , Sinpei Iijima , Yasuhiro Sugawara , Misuzu Kanai
IPC分类号： H01L218242
CPC分类号： H01L21/31604 , H01L21/02183 , H01L21/02271 , H01L21/02337 , H01L27/10814 , H01L27/10852 , H01L27/10882 , H01L27/10894 , H01L28/56 , H01L28/60 , H01L28/65
摘要： A semiconductor integrated circuit device including a memory cell comprising a memory cell selecting MISFET Qs formed on the main surface of a semiconductor substrate 1 and an information storage capacitor C that is connected in series to said memory cell selecting MISFET Qs, and that have a lower electrode 54, a capacitor insulator 58 and an upper electrode 59, wherein the lower electrode 54 is made of a conductive material containing ruthenium dioxide (RuO2) as principle ingredient and the capacitor insulator 58 is made of crystalline tantalum pentoxide. Thus, the capacitance required for the memory cells of a 256 Mbits DRAM or those of a DRAM of a later generation can be secured.

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