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1. 发明授权

US5504895A Method of managing data structure containing both persistent data and transient data 失效
标题翻译：管理包含持久性数据和瞬态数据的数据结构的方法
公开(公告)号：US5504895A
公开(公告)日：1996-04-02
申请号：US35572
申请日：1993-03-23
申请人： Takahiro Kurosawa , Masahiko Yoshimoto , Shigeki Shibayama , Ryuhei Uehara
发明人： Takahiro Kurosawa , Masahiko Yoshimoto , Shigeki Shibayama , Ryuhei Uehara
IPC分类号： G06F9/46 , G06F17/30
CPC分类号： G06F9/52 , Y10S707/99938
摘要： According to a data management method of managing shared data which is shared by a plurality of processes and data inherent in a process which exists during execution of one particular process and disappears when the process is finished, when each process fetches shared data from a data base into a memory, whether the shared data requires data inherent in the process is checked. Any inherent data of the process is determined, if necessity for that data is determined. The determined inherent data of the process is stored in the memory. A pointer for the inherent data of the process, which is stored in the memory, is stored into the fetched shared data in accordance with attributes inherent in the process requiring the inherent data of the process.
摘要翻译：根据多个处理共享的共享数据的管理方法和在一个特定处理的执行期间存在的处理中固有的数据，并且在处理完成时消失的数据管理方法，当每个处理从数据库中取出共享数据时进入存储器，检查共享数据是否需要该过程中固有的数据。确定该数据的必要性的过程的任何固有数据。所确定的处理的固有数据被存储在存储器中。存储在存储器中的用于存储在存储器中的进程的固有数据的指针根据需要该进程的固有数据的过程中固有的属性被存储到所获取的共享数据中。

2. 发明授权

US5894573A Program controlling method having transfer of code and data among programs and apparatus therefor 失效
标题翻译：程序控制方法，其程序和装置之间具有代码和数据的传送
公开(公告)号：US5894573A
公开(公告)日：1999-04-13
申请号：US812080
申请日：1997-03-06
申请人： Toshihiko Fukasawa , Masahiko Yoshimoto , Shigeki Shibayama , Takahiro Kurosawa
发明人： Toshihiko Fukasawa , Masahiko Yoshimoto , Shigeki Shibayama , Takahiro Kurosawa
IPC分类号： G06F9/46 , G06F9/445 , G06F9/54 , G06F15/16 , G06F15/177 , G06F9/44
CPC分类号： G06F9/44521 , G06F9/44552
摘要： An arrangement for executing a process in a data processing system using first and second programs each including executable codes and data in coordinated fashion in which a portion of the data and executable codes from the first program is provided to the second program during execution of the process. In execution of the process, portions of the data and executable codes provided by the first program to the second program are forcibly added or forcibly substituted and executed by the second program. The data and executable code portions are provided by injection and the injection and execution are conducted by imparting an acknowledgement of the addition or substitution and execution to the first program by the second program.
摘要翻译：一种用于在数据处理系统中执行处理的装置，其使用第一和第二程序，每个程序包括协调方式的可执行代码和数据，其中来自第一程序的数据和可执行代码的一部分在执行过程期间被提供给第二程序。在执行该处理时，由第一程序提供给第二程序的数据和可执行代码的部分被第二程序强制地增加或被强制替代和执行。通过注入提供数据和可执行代码部分，并且通过由第二程序向第一程序赋予加法或替换和执行的确认来执行注入和执行。

3. 发明授权

US5327538A Method of utilizing common buses in a multiprocessor system 失效
标题翻译：在多处理器系统中使用公共总线的方法
公开(公告)号：US5327538A
公开(公告)日：1994-07-05
申请号：US756547
申请日：1991-09-09
申请人： Kazumasa Hamaguchi , Shigeki Shibayama
发明人： Kazumasa Hamaguchi , Shigeki Shibayama
IPC分类号： G06F12/06 , G06F13/16 , G06F13/18 , G06F13/36 , G06F13/368
CPC分类号： G06F13/36 , G06F13/1652
摘要： In a multiprocessor system wherein a main storage is divided into a plurality of banks and a plurality of common buses are provided, in order to access the main storage. Each processor selects and acquires one of the buses in accordance with the utilization status of the common buses, and releases the bus after transmitting an access request utilizing the acquired bus. After processing the request, the main storage selects and acquires one of the buses in accordance with the utilization status of the common buses at that time independently of the bus which has transmitted the request, and transmits a result of the processing to the processor which has transmitted the access request utilizing the acquired bus.
摘要翻译：在其中主存储器被分成多个存储体并且提供多个公共总线的多处理器系统中，以便访问主存储器。每个处理器根据公共总线的使用情况选择并获取其中一条总线，并且在利用所获取的总线发送访问请求之后释放总线。在处理请求之后，主存储器独立于发送请求的总线，根据公共总线的使用状态选择并获取其中一条总线，并将处理结果发送给具有使用所获取的总线传送访问请求。

4. 发明授权

US4314333A Data processor 失效
标题翻译：数据处理器
公开(公告)号：US4314333A
公开(公告)日：1982-02-02
申请号：US22353
申请日：1979-03-20
申请人： Shigeki Shibayama , Kazuhide Iwata , Nobuo Okuda
发明人： Shigeki Shibayama , Kazuhide Iwata , Nobuo Okuda
IPC分类号： G06F9/22 , G06F9/28 , G06F9/318 , G06F9/38 , G06F15/16 , G06F13/06 , G06F7/00 , G06F9/06
CPC分类号： G06F9/30181 , G06F9/226 , G06F9/28 , G06F9/3879
摘要： A data processor used with a host computer is constructed by a plurality of memory units, at least one arithmetic and logic unit, a register file and a microprogram memory for storing microprograms to control these circuit components. The first field of each microinstruction of the microprogram is supplied to a first logic converting circuit of which the output signal drives each memory unit. The third field of the microinstruction is supplied to the second logic converting circuit of which the output signal causes the data stored in selected registers of the register file to be supplied to the arithmetic and logic unit. The arithmetic and logic unit operates upon the data supplied in accordance with the designation by the second field, and loads the result of the operation into the register specified by one of the outputs of the second logic converting circuit. Each logic converting circuit alters, in accordance to the control signal designated from the exterior, a combination of the corresponding field of a microinstruction.
摘要翻译：与主计算机一起使用的数据处理器由多个存储器单元，至少一个算术和逻辑单元，寄存器文件和微程序存储器构成，用于存储微程序以控制这些电路部件。微程序的每个微指令的第一场被提供给第一逻辑转换电路，其中输出信号驱动每个存储器单元。微指令的第三字段被提供给第二逻辑转换电路，其中输出信号使存储在寄存器文件的选定寄存器中的数据提供给算术和逻辑单元。算术和逻辑单元根据由第二场的指定提供的数据进行操作，并将操作结果加载到由第二逻辑转换电路的输出之一指定的寄存器中。每个逻辑转换电路根据从外部指定的控制信号改变微指令的相应字段的组合。

5. 发明授权

US4150434A Matrix arithmetic apparatus 失效
标题翻译：矩阵运算装置
公开(公告)号：US4150434A
公开(公告)日：1979-04-17
申请号：US794477
申请日：1977-05-06
申请人： Shigeki Shibayama , Tsutomu Kamimura
发明人： Shigeki Shibayama , Tsutomu Kamimura
IPC分类号： G06F15/78 , G06F15/34
CPC分类号： G06F15/8053
摘要： A matrix arithmetic apparatus which comprises a plurality of exclusive memories provided correspondingly to the respective items of a matrix or vector each including a plurality of elements in order to store element data corresponding to the elements. An arithmetic operation of Y=A.multidot.X+B is carried out with respect to the element data read out the memories wherein multiplication (A.multidot.X) and addition {(A.multidot.X)+B} of data representing the respective elements are undertaken by the exclusive arithmetic units by a pipe line system. Internal address computers corresponding to the memories are provided in order to determine a memory address of each of the memories from which a stored data is to be read out.
摘要翻译：一种矩阵运算装置，包括与矩阵或向量的各项相对应地设置的多个独占存储器，每个矩阵或向量包括多个元素，以便存储对应于该元素的元素数据。对于读出存储器的元素数据执行Y = AxX + B的算术运算，其中表示各个元素的数据的乘法（AxX）和加法{（AxX）+ B}由排他运算单元进行管线系统。提供与存储器相对应的内部地址计算机，以便确定存储数据将从其读出的每个存储器的存储器地址。

6. 发明授权

US5381466A Network systems 失效
标题翻译：网络系统
公开(公告)号：US5381466A
公开(公告)日：1995-01-10
申请号：US219750
申请日：1994-03-29
申请人： Shigeki Shibayama , Kazumasa Hamaguchi
发明人： Shigeki Shibayama , Kazumasa Hamaguchi
IPC分类号： H04M3/42 , H04M1/65 , H04M3/53 , H04M3/533 , H04M1/00 , H04M3/50
CPC分类号： H04M1/6505 , H04M3/5307 , H04M2201/60 , H04M3/533
摘要： This disclosure relates to a terminal unit for processing voice information which is adopted in a network system for transmitting and receiving voice information. This disclosure also pertains to a group of such terminal units. In a case where a voice converter is not provided in the terminal unit or when the use of the voice converter is suppressed, the terminal unit converts received voice information into a medium other than voice, for example, into characters, and thereby conveys it to a receiver. In a case where the terminal unit which receives the voice information is not provided with the function of converting the received voice information into a medium other than voice, the terminal unit requests another terminal unit within the terminal unit group to convert the voice information into a medium other than voice and thereby conveys it to a receiver.
摘要翻译：本公开涉及用于处理语音信息的终端单元，该终端单元在用于发送和接收语音信息的网络系统中采用。本公开还涉及一组这样的终端单元。在终端单元中没有设置语音转换器的情况下，或者当语音转换器的使用被抑制时，终端单元将接收到的语音信息转换成除了语音之外的介质，例如变成字符，从而将其传送到接收器在接收语音信息的终端单元不具有将接收到的语音信息转换为除语音之外的介质的功能的情况下，终端单元请求终端单元组内的另一终端单元将语音信息转换为媒体，而不是语音，从而将其传送到接收器。

7. 发明授权

US4482958A Data processing device for computed tomography system 失效
标题翻译：计算机断层摄影系统的数据处理装置
公开(公告)号：US4482958A
公开(公告)日：1984-11-13
申请号：US320566
申请日：1981-11-12
申请人： Nobutoshi Nakayama , Yukinobu Ito , Eitaro Nishihara , Kazuhide Iwata , Shigeki Shibayama
发明人： Nobutoshi Nakayama , Yukinobu Ito , Eitaro Nishihara , Kazuhide Iwata , Shigeki Shibayama
IPC分类号： A61B6/03 , G06F17/10 , G06Q50/22 , G06Q50/24 , G06T1/00 , G06T11/00 , G06F15/42
CPC分类号： G06T11/006 , Y10S378/901
摘要： A data processing device applied to a computed tomography system which examines a living body utilizing radiation of X-rays is disclosed. The X-rays which have penetrated the living body are converted into electric signals in a detecting section. The electric signals are acquired and converted from an analog form into a digital form in a data acquisition section, and then supplied to a matrix data-generating section included in the data processing device. By this matrix data-generating section are generated matrix data which correspond to a plurality of projection data. These matrix data are supplied to a partial sum-producing section. The partial sums respectively corresponding to groups of the matrix data are calculated in this partial sum-producing section and then supplied to an accumulation section. In this accumulation section, the final value corresponding to the total sum of the matrix data is calculated, whereby the calculation for image reconstruction is performed.
摘要翻译：公开了一种应用于利用X射线辐射检测生物体的计算机断层摄影系统的数据处理装置。已经穿透活体的X射线在检测部分被转换为电信号。在数据采集部分中将电信号从模拟形式获取并转换为数字形式，然后提供给包括在数据处理装置中的矩阵数据生成部分。由该矩阵数据生成部生成与多个投影数据对应的矩阵数据。这些矩阵数据被提供给部分求和部分。在该部分和产生部分中计算分别对应于矩阵数据的组的部分和，然后提供给累积部分。在该积累部中，计算与矩阵数据的总和对应的最终值，由此进行图像重构的计算。

8. 发明授权

US4231097A Apparatus for calculating a plurality of interpolation values 失效
标题翻译：用于计算多个内插值的装置
公开(公告)号：US4231097A
公开(公告)日：1980-10-28
申请号：US967420
申请日：1978-12-07
申请人： Shigeki Shibayama , Kazuhide Iwata , Nobuo Okuda
发明人： Shigeki Shibayama , Kazuhide Iwata , Nobuo Okuda
IPC分类号： G01N23/04 , A61B6/03 , G06F17/17 , G06T1/00 , G06T11/00 , G06F15/42
CPC分类号： G06T11/005 , G06F17/175 , G06T2211/421 , Y10S378/901
摘要： Apparatus for calculating a plurality of interpolation values is adapted to calculate linear interpolation values, consisting of a second data train, from a first data train and includes a memory for storing the first data train and a calculator for calculating the interpolation value from the corresponding two data in the first data train read out of the memory. The calculator comprises an n-bit register for designating those addresses of the memory where data to be read out of the upper m-bit section of the n-bit register is stored and for determining weighted factor data for calculating the interpolation value at the lower (n-m) bit section of the register, a calculating unit for calculating the interpolation value from the data read out of the memory and the weighting coefficient data, an adder for adding a position increment value for designating the adjacent interpolation value to the register each time each interpolation value is calculated at the calculating unit, and a counter stepped one count for each calculation of each interpolation value and adapted to send an end signal to a central processing unit when a predetermined number of counts are completed. The memory, register, adder and counter are controlled by the central processing unit.
摘要翻译：用于计算多个内插值的装置适于从第一数据序列计算由第二数据序列组成的线性内插值，并且包括用于存储第一数据序列的存储器和用于从相应的两个计算插值的计算器第一数据串中的数据从存储器中读出。该计算器包括一个n位寄存器，用于指定存储器中存储有从n位寄存器的上位m位读出的数据的那些地址，并确定加权因子数据，用于计算下位（nm）比特部分，用于根据从存储器读出的数据和加权系数数据计算内插值的计算单元，加法器，每次用于将用于指定相邻内插值的位置增量值添加到寄存器每个内插值在计算单元处计算，并且计数器对每个内插值的每次计算步进一个计数，并且当预定数量的计数完成时适于向中央处理单元发送结束信号。存储器，寄存器，加法器和计数器由中央处理器控制。

9. 发明授权

US5737568A Method and apparatus to control cache memory in multiprocessor system utilizing a shared memory 失效
标题翻译：在利用共享存储器的多处理器系统中控制高速缓冲存储器的方法和装置
公开(公告)号：US5737568A
公开(公告)日：1998-04-07
申请号：US393927
申请日：1995-02-21
申请人： Kazumasa Hamaguchi , Shigeki Shibayama
发明人： Kazumasa Hamaguchi , Shigeki Shibayama
IPC分类号： G06F12/08 , G06F13/14
CPC分类号： G06F12/0831
摘要： In a multiprocessor system having a shared memory containing the state of the data for every entry in each cache memory possessed by each processor. The state of the data is set to a "shared state" when the data is shared with other cache memories, and is set to a "shared stale state" when the data in the "shared state" becomes stale by updating performed in another cache memory. Each processor monitors a transaction generated on a bus, derives a data portion from the bus when it is in the same address as the data in the "shared stale state" of its own cache memory, thereby updating the data in the address and making the state of the data a "shared state".
摘要翻译：在具有共享存储器的多处理器系统中，该共享存储器包含由每个处理器拥有的每个高速缓冲存储器中的每个条目的数据的状态。当数据与其他高速缓冲存储器共享时，数据的状态被设置为“共享状态”，并且当通过在另一个高速缓存中执行的更新使“共享状态”中的数据变得陈旧时被设置为“共享陈旧状态” 记忆。每个处理器监视在总线上生成的事务，当它与其自己的高速缓冲存储器的“共享陈旧状态”中的数据处于相同的地址时，从总线导出数据部分，从而更新地址中的数据，并使数据状态为“共享状态”。

10. 发明授权

US4514826A Relational algebra engine 失效
标题翻译：关系代数引擎
公开(公告)号：US4514826A
公开(公告)日：1985-04-30
申请号：US364872
申请日：1982-04-02
申请人： Kazuhide Iwata , Shigeki Shibayama , Yutaka Hidai , Shigeru Oyanagi
发明人： Kazuhide Iwata , Shigeki Shibayama , Yutaka Hidai , Shigeru Oyanagi
IPC分类号： G06F7/02 , G06F7/24 , G06F17/30
CPC分类号： G06F17/30445 , Y10S707/99937
摘要： Disclosed is a relational algebra engine which has a sort engine, a merge engine, a control processor and a common bus. The sort engine has a plurality of first processing elements which are connected in series. Each first processing element includes first and second buffer memories, a first memory which has a FIFO function, and a first processor which sorts input data elements in accordance with a predetermined rule by using the first and second buffer memories and the first memory which has the FIFO function. The first and second buffer memories and the first memory which has the FIFO function are disposed in parallel. The merge engine has two second processing elements which are disposed in parallel. Each second processing element includes a third buffer memory, a second memory which has the FIFO function, a second processor which merges the data elements sorted in the sort engine by using the third buffer memory and the second memory which has the FIFO function and an output buffer memory which stores the data elements merged in the second processor. The third buffer memory is disposed parallel to the second memory which has the FIFO function.
摘要翻译：公开了一种具有分类引擎，合并引擎，控制处理器和公共总线的关系代数引擎。分类引擎具有串联连接的多个第一处理元件。每个第一处理元件包括第一和第二缓冲存储器，具有FIFO功能的第一存储器和通过使用第一和第二缓冲存储器和第一存储器按照预定规则对输入数据元素进行排序的第一处理器， FIFO功能。具有FIFO功能的第一和第二缓冲存储器和第一存储器并行设置。合并引擎具有平行布置的两个第二处理元件。每个第二处理元件包括第三缓冲存储器，具有FIFO功能的第二存储器，第二处理器，通过使用第三缓冲存储器和具有FIFO功能的第二存储器和输出端合并在排序引擎中排序的数据元素缓冲存储器，其存储合并在第二处理器中的数据元素。第三缓冲存储器平行于具有FIFO功能的第二存储器。

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