专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5327538A Method of utilizing common buses in a multiprocessor system 失效
标题翻译：在多处理器系统中使用公共总线的方法
公开(公告)号：US5327538A
公开(公告)日：1994-07-05
申请号：US756547
申请日：1991-09-09
申请人： Kazumasa Hamaguchi , Shigeki Shibayama
发明人： Kazumasa Hamaguchi , Shigeki Shibayama
IPC分类号： G06F12/06 , G06F13/16 , G06F13/18 , G06F13/36 , G06F13/368
CPC分类号： G06F13/36 , G06F13/1652
摘要： In a multiprocessor system wherein a main storage is divided into a plurality of banks and a plurality of common buses are provided, in order to access the main storage. Each processor selects and acquires one of the buses in accordance with the utilization status of the common buses, and releases the bus after transmitting an access request utilizing the acquired bus. After processing the request, the main storage selects and acquires one of the buses in accordance with the utilization status of the common buses at that time independently of the bus which has transmitted the request, and transmits a result of the processing to the processor which has transmitted the access request utilizing the acquired bus.
摘要翻译：在其中主存储器被分成多个存储体并且提供多个公共总线的多处理器系统中，以便访问主存储器。每个处理器根据公共总线的使用情况选择并获取其中一条总线，并且在利用所获取的总线发送访问请求之后释放总线。在处理请求之后，主存储器独立于发送请求的总线，根据公共总线的使用状态选择并获取其中一条总线，并将处理结果发送给具有使用所获取的总线传送访问请求。

2. 发明授权

US5381466A Network systems 失效
标题翻译：网络系统
公开(公告)号：US5381466A
公开(公告)日：1995-01-10
申请号：US219750
申请日：1994-03-29
申请人： Shigeki Shibayama , Kazumasa Hamaguchi
发明人： Shigeki Shibayama , Kazumasa Hamaguchi
IPC分类号： H04M3/42 , H04M1/65 , H04M3/53 , H04M3/533 , H04M1/00 , H04M3/50
CPC分类号： H04M1/6505 , H04M3/5307 , H04M2201/60 , H04M3/533
摘要： This disclosure relates to a terminal unit for processing voice information which is adopted in a network system for transmitting and receiving voice information. This disclosure also pertains to a group of such terminal units. In a case where a voice converter is not provided in the terminal unit or when the use of the voice converter is suppressed, the terminal unit converts received voice information into a medium other than voice, for example, into characters, and thereby conveys it to a receiver. In a case where the terminal unit which receives the voice information is not provided with the function of converting the received voice information into a medium other than voice, the terminal unit requests another terminal unit within the terminal unit group to convert the voice information into a medium other than voice and thereby conveys it to a receiver.
摘要翻译：本公开涉及用于处理语音信息的终端单元，该终端单元在用于发送和接收语音信息的网络系统中采用。本公开还涉及一组这样的终端单元。在终端单元中没有设置语音转换器的情况下，或者当语音转换器的使用被抑制时，终端单元将接收到的语音信息转换成除了语音之外的介质，例如变成字符，从而将其传送到接收器在接收语音信息的终端单元不具有将接收到的语音信息转换为除语音之外的介质的功能的情况下，终端单元请求终端单元组内的另一终端单元将语音信息转换为媒体，而不是语音，从而将其传送到接收器。

3. 发明授权

US5737568A Method and apparatus to control cache memory in multiprocessor system utilizing a shared memory 失效
标题翻译：在利用共享存储器的多处理器系统中控制高速缓冲存储器的方法和装置
公开(公告)号：US5737568A
公开(公告)日：1998-04-07
申请号：US393927
申请日：1995-02-21
申请人： Kazumasa Hamaguchi , Shigeki Shibayama
发明人： Kazumasa Hamaguchi , Shigeki Shibayama
IPC分类号： G06F12/08 , G06F13/14
CPC分类号： G06F12/0831
摘要： In a multiprocessor system having a shared memory containing the state of the data for every entry in each cache memory possessed by each processor. The state of the data is set to a "shared state" when the data is shared with other cache memories, and is set to a "shared stale state" when the data in the "shared state" becomes stale by updating performed in another cache memory. Each processor monitors a transaction generated on a bus, derives a data portion from the bus when it is in the same address as the data in the "shared stale state" of its own cache memory, thereby updating the data in the address and making the state of the data a "shared state".
摘要翻译：在具有共享存储器的多处理器系统中，该共享存储器包含由每个处理器拥有的每个高速缓冲存储器中的每个条目的数据的状态。当数据与其他高速缓冲存储器共享时，数据的状态被设置为“共享状态”，并且当通过在另一个高速缓存中执行的更新使“共享状态”中的数据变得陈旧时被设置为“共享陈旧状态” 记忆。每个处理器监视在总线上生成的事务，当它与其自己的高速缓冲存储器的“共享陈旧状态”中的数据处于相同的地址时，从总线导出数据部分，从而更新地址中的数据，并使数据状态为“共享状态”。

4. 发明授权

US5933261A Information processing method and system 失效
标题翻译：信息处理方法和系统
公开(公告)号：US5933261A
公开(公告)日：1999-08-03
申请号：US672022
申请日：1996-06-26
申请人： Toshiyuki Fukui , Kazumasa Hamaguchi , Tomohiko Shimoyama , Shuichi Nakamura
发明人： Toshiyuki Fukui , Kazumasa Hamaguchi , Tomohiko Shimoyama , Shuichi Nakamura
IPC分类号： G06F15/173 , H04J14/02
CPC分类号： G06F15/17381
摘要： An information processing system has a plurality of nodes each including one or more CPUs that utilize monitoring of a common bus, wherein the plurality of nodes are connected to one another by a connection path that cannot monitor information on an internal bus in each node. Information required to perform synchronized operation in a node or among nodes is transmitted to an arbiter via an optical fiber serving as a transmission path different from the connection path, and part of this information is again distributed from the arbiter to each of the nodes based upon the information. The system operates in such a manner that the information is reflected in its own node based upon the re-distributed information. Further, in order to perform the synchronized operation among CPUs based upon the re-distributed information, the system controls the information to be distributed from each node to arbiter. Thus, when an operation for maintaining synchronization among CPUs is performed, the present invention enables the system to reduce processing which accompanies synchronizing operation by CPUs across nodes and improve the processing capability of the entire system.
摘要翻译：信息处理系统具有多个节点，每个节点包括利用对公共总线的监控的一个或多个CPU，其中多个节点通过不能监视每个节点内部总线上的信息的连接路径相互连接。在节点或节点之间执行同步操作所需的信息经由用作不同于连接路径的传输路径的光纤被发送到仲裁器，并且该信息的一部分再次从仲裁器分配到每个节点信息。该系统以这样一种方式运行，即基于重新发布的信息将信息反映在其自己的节点中。此外，为了基于重新分发的信息来执行CPU之间的同步操作，系统控制从每个节点分发给仲裁器的信息。因此，当执行用于保持CPU之间的同步的操作时，本发明使得系统能够减少伴随着跨节点的CPU的同步操作的处理，并提高整个系统的处理能力。

5. 发明授权

US5602663A Information processing apparatus for multiplex transmission of signal for arbitration and signal for data transfer 失效
标题翻译：信号处理装置，用于多路传输用于仲裁的信号和用于数据传送的信号
公开(公告)号：US5602663A
公开(公告)日：1997-02-11
申请号：US341877
申请日：1994-11-15
申请人： Kazumasa Hamaguchi , Atsushi Date , Masato Kosugi , Toshiyuki Fukui
发明人： Kazumasa Hamaguchi , Atsushi Date , Masato Kosugi , Toshiyuki Fukui
IPC分类号： G06F15/173 , G06F13/00 , H04J1/05 , H04L12/44 , H04Q11/00 , H04J14/02
CPC分类号： H04L12/44 , H04Q11/0062 , H04Q11/0066 , H04Q2011/0015 , H04Q2011/0039 , H04Q2011/0086
摘要： An information processing apparatus has a plurality of computational nodes including a multiplexer and a demultiplexer. A concentrator is connected to the nodes and simultaneously transmits multiplexed signals thereto. An arbiter arbitrates the use of a transmission line for data transfer, with the arbitration and data transfer signals being multiplexed.
摘要翻译：信息处理装置具有包括多路复用器和解复用器的多个计算节点。集中器连接到节点并且同时向其发送多路复用信号。仲裁者对仲裁和数据传输信号进行多路复用来仲裁传输线用于数据传输。

6. 发明授权

US5995751A Information processing apparatus 失效
标题翻译：信息处理装置
公开(公告)号：US5995751A
公开(公告)日：1999-11-30
申请号：US795454
申请日：1997-02-04
申请人： Masato Kosugi , Atsushi Date , Kazumasa Hamaguchi , Toshiyuki Fukui
发明人： Masato Kosugi , Atsushi Date , Kazumasa Hamaguchi , Toshiyuki Fukui
IPC分类号： G06F9/38 , G06F9/312 , G06F9/315 , G06F15/16 , G06F15/78 , G06F15/80 , G06T1/20 , H04N7/24 , H04N19/00 , H04N19/423 , H04N19/436 , H04N19/463 , H04N19/625 , H04N19/70 , H04N19/91 , G06F1/12
CPC分类号： G06F9/30032 , G06F15/8053 , G06F9/30043 , G06F9/3869
摘要： An information processing apparatus in which continuous data of a plurality of series in which the contents of the data of each series are related to each other with respect to time is pipeline processed by a data processing system. The apparatus comprises a plurality of sync generation circuits which correspond to the plurality of series and each of which generate sync signals to instruct timings for the data transfer and data process of each series, and a sync control circuit for controlling generation situations of the sync signals from the plurality of sync generation circuits in accordance with a degree of progress of the data process of each series in the data processing system so that the data of each series can be processed in the data processing system without losing the time-dependent relation.
摘要翻译：一种信息处理装置，其中数据处理系统进行流水线处理，其中每个系列的数据的内容相对于时间彼此相关的多个系列的连续数据。该装置包括对应于多个系列的多个同步产生电路，并且每个同步产生电路产生同步信号以指示每个系列的数据传输和数据处理的定时，以及用于控制同步信号的产生情况的同步控制电路根据数据处理系统中的每个系列的数据处理的进行程度从多个同步产生电路中获取数据，使得可以在数据处理系统中处理每个系列的数据而不失去时间依赖关系。

7. 发明授权

US5923339A Higher-speed parallel processing 失效
标题翻译：更高速的并行处理
公开(公告)号：US5923339A
公开(公告)日：1999-07-13
申请号：US978813
申请日：1997-11-26
申请人： Atsushi Date , Kazumasa Hamaguchi , Masato Kosugi , Toshiyuki Fukui
发明人： Atsushi Date , Kazumasa Hamaguchi , Masato Kosugi , Toshiyuki Fukui
IPC分类号： H04N5/91 , G06F15/16 , G06F15/78 , G06T1/20 , H04N7/24 , H04N19/00 , H04N19/42 , H04N19/423 , H04N19/625 , H04N19/85 , H04N19/91 , G06F15/80
CPC分类号： G06F15/8053
摘要： An information processing apparatus which processes a large amount of data at high speed. The synchronizing signal has a cycle including a transfer period and a processing period. In the transfer period, data is transferred, e.g., from a data input unit to a first memory, and from the first memory to a second memory. In the processing period, the data input unit reads data for one frame of a digital video image, and a data output unit displays an image based on the image data. Processors respectively perform predetermined processing upon data stored in a memory connected to the processor. Thus, within one cycle of the synchronizing signal, processing is completed at respective stages from input to output. Note that the connection between the memories and the processors may be changed for performing the processing at the respective stages without data transfer. In this case, data transfer time can be saved.
摘要翻译：一种高速处理大量数据的信息处理装置。同步信号具有包括传送周期和处理周期的周期。在传送期间，数据例如从数据输入单元传送到第一存储器，并从第一存储器传送到第二存储器。在处理期间，数据输入部读取数字视频图像的一帧的数据，数据输出部根据图像数据显示图像。处理器分别对存储在连接到处理器的存储器中的数据执行预定处理。因此，在同步信号的一个周期内，在从输入到输出的各个阶段完成处理。注意，可以改变存储器和处理器之间的连接，以在不进行数据传送的情况下在各个阶段执行处理。在这种情况下，可以节省数据传输时间。

8. 发明授权

US5577218A Memory access control method wherein block access is performed as a sequential access to an address updated by incrementation 失效
标题翻译：存储器访问控制方法，其中块访问被执行为对通过递增更新的地址的顺序访问
公开(公告)号：US5577218A
公开(公告)日：1996-11-19
申请号：US428799
申请日：1995-04-24
申请人： Kazumasa Hamaguchi
发明人： Kazumasa Hamaguchi
IPC分类号： G06F12/02 , G11C11/401 , G06F12/06
CPC分类号： G06F12/0215
摘要： In a system having a memory unit using a memory for a block transfer function, access requested from a processor is executed by using the block transfer function even if the requested access is not block access to be conducted with respect to a block, provided that block transfer is possible.
摘要翻译：在具有使用块传输功能的存储器的存储器单元的系统中，即使所请求的访问不是相对于块执行块访问，也通过使用块传送函数来执行从处理器请求的访问，只要块转移是可能的。

9. 发明授权

US6138217A Method and apparatus for cache coherency in an interconnecting network 失效
标题翻译：互连网络中高速缓存一致性的方法和装置
公开(公告)号：US6138217A
公开(公告)日：2000-10-24
申请号：US976236
申请日：1997-11-21
申请人： Kazumasa Hamaguchi
发明人： Kazumasa Hamaguchi
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0813 , G06F12/0815 , G06F12/0817 , G06F2212/2542
摘要： In a data processing system where a plurality of nodes, each having a plurality of processors and cache memories associated with each of the processors, are connected via a bus, tag information is added to each data block stored in the cache memories. The tag information has state information which includes information (INTERNODE-SHARED) indicative of whether or not the data block is cached in another node. When a write-access is transmitted to the data block in the cache memory, if the state information added to the data block is INTERNODE-SHARED, invalidation of the data block is requested to the other node.
摘要翻译：在数据处理系统中，每个具有多个处理器的节点和与每个处理器相关联的高速缓冲存储器的多个节点经由总线连接，标签信息被添加到存储在高速缓冲存储器中的每个数据块。标签信息具有指示数据块是否被缓存在另一节点中的信息（INTERNODE-SHARED）的状态信息。当向高速缓冲存储器中的数据块发送写入访问时，如果添加到数据块的状态信息是INTERNODE-SHARED，则向另一个节点请求数据块的无效。

10. 发明授权

US6078337A Maintaining consistency of cache memory data by arbitrating use of a connection route by plural nodes 失效
标题翻译：通过仲裁多个节点使用连接路由来保持缓存存储器数据的一致性
公开(公告)号：US6078337A
公开(公告)日：2000-06-20
申请号：US526328
申请日：1995-09-11
申请人： Toshiyuki Fukui , Atsushi Date , Kazumasa Hamaguchi , Masato Kosugi
发明人： Toshiyuki Fukui , Atsushi Date , Kazumasa Hamaguchi , Masato Kosugi
IPC分类号： G06F12/08 , G06F13/16
CPC分类号： G06F12/0815 , G06F12/0813 , G06F2212/2542
摘要： In a system in which a plurality of nodes are connected using a light wavelength multiplexing connection route which can simultaneously connect nodes using light beams of a plurality of different wavelengths, each node has a cache memory for holding data in memories in other nodes. Some or all of the pieces of information required for data transfer in one node or between the nodes are transferred from the node to an arbiter used in use arbitration of the connection route via one of arbitration optical signal routes for respectively connecting the arbiter and the nodes. The arbiter distributes the transferred information to other nodes, and each node updates the contents of its cache memory on the basis of the distributed information.
摘要翻译：在使用可以使用多个不同波长的光束同时连接节点的光波长多路复用连接路径来连接多个节点的系统中，每个节点具有用于将数据保存在其他节点中的存储器中的高速缓冲存储器。在一个节点或节点之间进行数据传输所需的一些或全部信息是通过用于分别连接仲裁器和节点的仲裁光信号路由之一从节点传送到在连接路由的使用仲裁中使用的仲裁器。仲裁器将传送的信息分发到其他节点，每个节点根据分布式信息更新其高速缓冲存储器的内容。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式