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1. 发明申请

US20100237438A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100237438A1
公开(公告)日：2010-09-23
申请号：US12706056
申请日：2010-02-16
申请人： Takafumi IKEDA , Takahito Nakazawa , Hideaki Maekawa , Yuuichi Tatsumi , Toshifumi Minami
发明人： Takafumi IKEDA , Takahito Nakazawa , Hideaki Maekawa , Yuuichi Tatsumi , Toshifumi Minami
IPC分类号： H01L29/06
CPC分类号： H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a circuit element region formed on a semiconductor substrate, and a protective pattern formed so as to surround the circuit element region. The protective pattern comprises a first element separation region formed on the semiconductor substrate, a second element separation region formed on the semiconductor substrate and having a width smaller than that of the first element separation region, a first element region formed between the first element separation region and the second element separation region, a first gate layer formed on the first element separation region, a wiring layer formed on the first gate layer, a passivation layer formed above the wiring layer, a second element region, an insulation film formed on the second element region, and a second gate layer formed on the insulation film, the first element separation region, the first element region, the second element separation region and the second element region being located in this order from the nearer side of the circuit element region.
摘要翻译：半导体器件具有形成在半导体衬底上的电路元件区域和形成为围绕电路元件区域的保护图案。保护图案包括形成在半导体衬底上的第一元件分离区域，形成在半导体衬底上的第二元件分离区域，其宽度小于第一元件分离区域的宽度;第一元素区域，形成在第一元素分离区域和第二元件分离区域，形成在第一元件分离区域上的第一栅极层，形成在第一栅极层上的布线层，形成在布线层上方的钝化层，第二元素区域，形成在第二栅极层上的绝缘膜元件区域和形成在绝缘膜上的第二栅极层，第一元件分离区域，第一元件区域，第二元件分离区域和第二元件区域从电路元件区域的更靠近的方向定位。

2. 发明申请

US20120074103A1 SEAM WELDING WARPAGE PREVENTION METHOD AND APPARATUS 有权
标题翻译：焊接保护预防方法和装置
公开(公告)号：US20120074103A1
公开(公告)日：2012-03-29
申请号：US13233617
申请日：2011-09-15
申请人： Eisaku HASEGAWA , Mitsugu KANEKO , Takafumi IKEDA , Haruhiko KOBAYASHI
发明人： Eisaku HASEGAWA , Mitsugu KANEKO , Takafumi IKEDA , Haruhiko KOBAYASHI
IPC分类号： B23K11/08
CPC分类号： B23K11/08 , B23K11/06 , B23K11/061 , B23K11/16 , B23K11/20 , B23K2103/04 , B23K2103/18
摘要： It is an object of the present invention to provide a seam welding warpage prevention method and apparatus capable of preventing warpage caused by cooling contraction after welding, in a case where workpieces are different from one another in material and thickness, and thus not uniform in thermal contraction. In the seam welding warpage prevention method for welding a plurality of workpieces W1 and W2 that are not uniform in thermal contraction with respect to an energizing direction, the workpieces W1 and W2 are clamped with a pair of roller electrodes 23 and 33 while applying current. The welding is performed in a state where the roller electrode 33 that abuts on the workpiece W2 having higher thermal contraction is offset in an advancing direction ahead of the roller electrode 23 that abuts on the workpiece W1 having lower thermal contraction.
摘要翻译：本发明的目的是提供一种能够防止焊接后的冷却收缩引起的翘曲的缝焊翘曲防止方法和装置，在工件在材料和厚度上彼此不同的情况下，因此不均匀的热收缩在用于焊接相对于通电方向的热收缩不均匀的多个工件W1和W2的焊缝翘曲防止方法中，工件W1和W2在施加电流的同时用一对辊电极23和33夹紧。焊接是在接触具有较高热收缩的工件W2的辊电极33在靠近具有较低热收缩的工件W1的辊电极23之前的前进方向上偏移的状态下进行的。

3. 发明申请

US20110204426A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110204426A1
公开(公告)日：2011-08-25
申请号：US12871362
申请日：2010-08-30
申请人： Shoko KIKUCHI , Takafumi IKEDA , Kazuhiro SHIMIZU
发明人： Shoko KIKUCHI , Takafumi IKEDA , Kazuhiro SHIMIZU
IPC分类号： H01L27/105
CPC分类号： H01L29/42324 , H01L21/28273 , H01L29/7881
摘要： According to one embodiment, a semiconductor device includes a stacked structure that is formed by laminating a first insulating film, first conductive layer, second insulating film and second conductive layer on a semiconductor substrate and in which the first and second conductive layers are connected with a via electrically, an interlayer insulating film formed to electrically separate the second conductive layer into a first region including a connecting portion with the first conductive layer and a second region that does not include the connecting portion, a first contact plug formed on the first region and a second contact plug formed on the second region. An isolation insulating film is buried in portions of the substrate, first insulating film and first conductive layer in one peripheral portion on the second region side of the stacked structure and the second contact plug is formed above the isolation insulating film.
摘要翻译：根据一个实施例，半导体器件包括通过在半导体衬底上层叠第一绝缘膜，第一导电层，第二绝缘膜和第二导电层而形成的层叠结构，其中第一和第二导电层与通过电连接，形成为将第二导电层电分离成包括与第一导电层的连接部分的第一区域和不包括连接部分的第二区域的层间绝缘膜，形成在第一区域上的第一接触插塞和形成在第二区域上的第二接触塞。隔离绝缘膜被埋置在层叠结构的第二区域侧的一个周边部分中的基板，第一绝缘膜和第一导电层的部分中，并且第二接触插塞形成在隔离绝缘膜上方。

4. 发明申请

US20090035907A1 METHOD OF FORMING STACKED GATE STRUCTURE FOR SEMICONDUCTOR MEMORY 审中-公开
标题翻译：形成半导体存储器堆叠结构的方法
公开(公告)号：US20090035907A1
公开(公告)日：2009-02-05
申请号：US12035829
申请日：2008-02-22
申请人： Takafumi IKEDA
发明人： Takafumi IKEDA
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L29/66825 , H01L29/7883
摘要： A method of manufacturing a nonvolatile semiconductor memory comprising: forming a gate insulating film formed on a surface of a semiconductor substrate; forming a source region and a drain region in the semiconductor substrate; forming a floating gate electrode on the gate insulating film; forming a inter-gate insulating film on the floating gate electrode; forming a control gate electrode on the inter-gate insulating film; forming a source contact region wherein the source contact region is electrically contact to said source region, and top part of said source contact region is lower than bottom part of said control gate electrode.
摘要翻译：一种制造非易失性半导体存储器的方法，包括：形成在半导体衬底的表面上的栅极绝缘膜; 在所述半导体衬底中形成源区和漏区; 在栅极绝缘膜上形成浮栅电极; 在所述浮栅电极上形成栅间绝缘膜; 在所述栅极间绝缘膜上形成控制栅电极; 形成源极接触区域，其中所述源极接触区域与所述源极区域电接触，并且所述源极接触区域的顶部部分低于所述控制栅极电极的底部。

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