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1. 发明授权

US5901101A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5901101A
公开(公告)日：1999-05-04
申请号：US919505
申请日：1997-08-28
申请人： Takaaki Suzuki , Masao Nakano , Hiroyoshi Tomita , Yasuharu Sato , Kotoku Sato , Nobutaka Taniguchi
发明人： Takaaki Suzuki , Masao Nakano , Hiroyoshi Tomita , Yasuharu Sato , Kotoku Sato , Nobutaka Taniguchi
IPC分类号： G11C11/403 , G11C11/406 , G11C11/407 , G11C7/00
CPC分类号： G11C11/406
摘要： In a semiconductor memory device operable in synchronism with a clock signal externally supplied thereto, there are provided a first part which detects a state of a predetermined signal after a given command is input to the semiconductor memory; and a second part which sets, on the basis of the state of the predetermined signal, the semiconductor memory device to a self-refresh mode in which a refresh operation is carried out without an external signal.
摘要翻译：在与外部提供给其的时钟信号同步操作的半导体存储器件中，提供了第一部分，其在将给定命令输入到半导体存储器之后检测预定信号的状态; 以及第二部分，其基于预定信号的状态将半导体存储器件设置为在没有外部信号的情况下执行刷新操作的自刷新模式。

2. 发明授权

US6078514A Semiconductor device and semiconductor system for high-speed data transfer 失效
标题翻译：半导体器件和半导体系统，用于高速数据传输
公开(公告)号：US6078514A
公开(公告)日：2000-06-20
申请号：US61023
申请日：1998-04-16
申请人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Takaaki Suzuki , Hiroyoshi Tomita , Toshiya Uchida , Yasuharu Sato , Atsushi Hatakeyama , Masato Matsumiya , Yasurou Matsuzaki
发明人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Takaaki Suzuki , Hiroyoshi Tomita , Toshiya Uchida , Yasuharu Sato , Atsushi Hatakeyama , Masato Matsumiya , Yasurou Matsuzaki
IPC分类号： G11C11/41 , G11C7/10 , G11C7/22 , G11C11/401 , H01L21/60 , H01L25/00 , H01L27/10 , H01L25/04 , H01L23/36
CPC分类号： H01L23/60 , G11C7/1006 , G11C7/22 , H01L24/49 , H01L25/0655 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/49175 , H01L24/48 , H01L27/0266 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/1305 , H01L2924/13091 , H01L2924/30105
摘要： A semiconductor system includes at least one logic chip and at least one memory chip arranged such that one side of the at least one memory chip faces one side of the at least one logic chip. The semiconductor system further includes first input/output nodes, provided for the at least one logic chip, for data transfer with an adjacent memory chip, second input/output nodes, provided for the at least one memory chip, for data transfer with an adjacent logic chip, and a package housing the at least one logic chip and the at least one memory chip, wherein the first input/output nodes are arranged along the one side of the at least one logic chip, and the second input/output nodes are arranged along the one side of the at least one memory chip.
摘要翻译：半导体系统包括至少一个逻辑芯片和布置成使得至少一个存储器芯片的一侧面向至少一个逻辑芯片的一侧的至少一个存储器芯片。所述半导体系统还包括为所述至少一个逻辑芯片提供的用于与相邻存储器芯片进行数据传输的第一输入/输出节点，为所述至少一个存储器芯片提供的第二输入/输出节点，用于与相邻的逻辑芯片以及容纳所述至少一个逻辑芯片和所述至少一个存储器芯片的封装，其中所述第一输入/输出节点沿着所述至少一个逻辑芯片的一侧布置，并且所述第二输入/输出节点是沿着至少一个存储器芯片的一侧布置。

3. 发明授权

US06961830B2 Semiconductor memory device with fast masking process in burst write mode 失效
标题翻译：具有突发写入模式的快速掩蔽处理的半导体存储器件
公开(公告)号：US06961830B2
公开(公告)日：2005-11-01
申请号：US10327096
申请日：2002-12-24
申请人： Hitoshi Ikeda , Yasuharu Sato , Takaaki Suzuki , Toshiya Uchida , Kotoku Sato
发明人： Hitoshi Ikeda , Yasuharu Sato , Takaaki Suzuki , Toshiya Uchida , Kotoku Sato
IPC分类号： G11C11/407 , G11C7/10 , G11C7/22 , G11C11/401 , G06F13/28
CPC分类号： G11C7/22 , G11C7/1006 , G11C2207/229
摘要： A semiconductor memory device has a burst write mode in which predetermined plural command signals are input through a plurality of command pads and a mask control operation in the burst write mode is performed in response to the command signals. Therefore, the mask control in burst write mode is increased in speed to give an improved data transfer rate.
摘要翻译：半导体存储器件具有突发写入模式，其中通过多个命令焊盘输入预定的多个命令信号，并且响应于命令信号执行脉冲串写入模式中的掩码控制操作。因此，突发写入模式中的掩码控制的速度提高，从而提高数据传输速率。

4. 发明授权

US06535965B1 Semiconductor memory device with fast masking process in burst write mode 有权
标题翻译：具有突发写入模式的快速掩蔽处理的半导体存储器件
公开(公告)号：US06535965B1
公开(公告)日：2003-03-18
申请号：US09559099
申请日：2000-04-27
申请人： Hitoshi Ikeda , Yasuharu Sato , Takaaki Suzuki , Toshiya Uchida , Kotoku Sato
发明人： Hitoshi Ikeda , Yasuharu Sato , Takaaki Suzuki , Toshiya Uchida , Kotoku Sato
IPC分类号： G06F1200
CPC分类号： G11C7/22 , G11C7/1006 , G11C2207/229
摘要： A semiconductor memory device has a burst write mode in which predetermined plural command signals are input through a plurality of command pads and a mask control operation in the burst write mode is performed in response to the command signals. Therefore, the mask control in burst write mode is increased in speed to give an improved data transfer rate.
摘要翻译：半导体存储器件具有突发写入模式，其中通过多个命令焊盘输入预定的多个命令信号，并且响应于命令信号执行脉冲串写入模式中的掩码控制操作。因此，突发写入模式中的掩码控制的速度提高，从而提高数据传输速率。

5. 发明授权

US06724675B2 Semiconductor memory device and electronic apparatus 有权
标题翻译：半导体存储器件和电子设备
公开(公告)号：US06724675B2
公开(公告)日：2004-04-20
申请号：US10352985
申请日：2003-01-29
申请人： Akihiro Funyu , Shinya Fujioka , Hitoshi Ikeda , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato , Yasurou Matsuzaki
发明人： Akihiro Funyu , Shinya Fujioka , Hitoshi Ikeda , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato , Yasurou Matsuzaki
IPC分类号： G11C800
CPC分类号： G11C7/1042 , G11C7/1063 , G11C7/20 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/4072
摘要： A semiconductor memory device, such as a DRAM, which needs to be refreshed for retaining data, is provided with a storing portion for storing data therein, and a busy signal outputting portion outputting a busy signal during the refresh operation.
摘要翻译：为了保存数据而需要刷新的诸如DRAM的半导体存储器件提供有用于存储数据的存储部分和在刷新操作期间输出忙信号的忙信号输出部分。

6. 发明授权

US6144616A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US6144616A
公开(公告)日：2000-11-07
申请号：US429472
申请日：1999-10-29
申请人： Takaaki Suzuki , Kotoku Sato
发明人： Takaaki Suzuki , Kotoku Sato
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： G11C7/1072
摘要： A semiconductor memory device operating in synchronism with a clock includes an address latch&comparator part latching a first address signal associated with a write command and comparing the first address signal with a second address signal associated with a read command. A write data buffer part holds a data signal associated with the write command. The data signal held in the write data buffer part is read as a data signal requested by the read command when the first and second address signals coincide with each other.
摘要翻译：与时钟同步工作的半导体存储器件包括地址锁存器和比较器部件，其锁存与写入命令相关联的第一地址信号，并将第一地址信号与与读取命令相关联的第二地址信号进行比较。写数据缓冲器部分保存与写命令相关联的数据信号。当第一和第二地址信号彼此一致时，保持在写入数据缓冲器部分中的数据信号被读取为由读取命令请求的数据信号。

7. 发明授权

US06172938B2 Electronic instrument and semiconductor memory device 有权
标题翻译：电子仪器和半导体存储器件
公开(公告)号：US06172938B2
公开(公告)日：2001-01-09
申请号：US09338597
申请日：1999-06-23
申请人： Takaaki Suzuki , Masao Taguchi , Kotoku Sato
发明人： Takaaki Suzuki , Masao Taguchi , Kotoku Sato
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1072 , G11C11/4076
摘要： An electronic instrument includes a memory device, clock lines through which complementary clock signals are transmitted to be used for synchronization of a data output operation and a data input operation for the memory device, and strobe signal lines through which a first output strobe signal, a second output strobe signal, a first input strobe signal and a second input strobe signal are transmitted to be used to settle output data from the memory device in the data output operation and to settle input data supplied to the memory device, the first and second output strobe signals being in complementary relation to each other, the first and second input strobe signals being in complementary relation to each other.
摘要翻译：一种电子仪器，包括：存储器件，传输互补时钟信号的时钟线，用于数据输出操作的同步和存储器件的数据输入操作;以及选通信号线，第一输出选通信号，发送第二输出选通信号，第一输入选通信号和第二输入选通信号，以在数据输出操作中用于建立来自存储器件的输出数据，并且提供提供给存储器件的输入数据，第一和第二输出选通信号彼此互补，第一和第二输入选通信号彼此互补。

8. 发明授权

US06735141B2 Semiconductor memory device having an SRAM and a DRAM on a single chip 失效
标题翻译：在单个芯片上具有SRAM和DRAM的半导体存储器件
公开(公告)号：US06735141B2
公开(公告)日：2004-05-11
申请号：US09917913
申请日：2001-07-31
申请人： Hitoshi Ikeda , Akihiro Funyu , Shinya Fujioka , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato
发明人： Hitoshi Ikeda , Akihiro Funyu , Shinya Fujioka , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato
IPC分类号： G11C700
CPC分类号： G11C11/005
摘要： A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.
摘要翻译：半导体存储器件包括设置在芯片上的SRAM，SRAM包括SRAM单元阵列。在芯片上提供DRAM，DRAM包括DRAM单元阵列。地址输入电路接收地址信号，地址信号具有第一部分和第二部分，第一部分承载提供用于访问SRAM和DRAM单元阵列之一中的存储单元之一的行列地址信息的唯一值，第二部分承载提供用于选择SRAM和DRAM之一的SRAM / DRAM地址信息的唯一值。

9. 发明授权

US06629224B1 Method for operating a semiconductor memory device having a plurality of operating modes for controlling an internal circuit 有权
标题翻译：一种用于操作具有用于控制内部电路的多种操作模式的半导体存储器件的方法
公开(公告)号：US06629224B1
公开(公告)日：2003-09-30
申请号：US09562739
申请日：2000-05-01
申请人： Takaaki Suzuki , Toshiya Uchida , Kotoku Sato , Yoshimasa Yagishita
发明人： Takaaki Suzuki , Toshiya Uchida , Kotoku Sato , Yoshimasa Yagishita
IPC分类号： G06F1200
CPC分类号： G11C11/406 , G11C5/066 , G11C11/40603 , G11C11/40611
摘要： Signals supplied to predetermined terminals are accepted as commands at a plurality of times, the number of operating modes is sequentially narrowed down based on the command each time and an internal circuit is controlled according to the narrowed operating modes. Since the information necessary for determining an operating mode is accepted at a plurality of times, the number of terminals necessary for inputting commands can be reduced. In particular, in case of inputting commands at a dedicated terminal, its input pads, input circuits, or the like are no longer be required so that the chip size can be reduced. The reduction is accomplished by reducing the number of terminals, which gives limits to the package size. The command controlling circuit with a plurality of accepting circuits is comprised. Each of the accepting circuits respectively accepts signals, supplied at a plurality of times, each time. In other words, in accordance with the timing of the signal supplement, a different accepting circuit is respectively operated and the internal circuit is controlled. Accordingly, a command controlling circuit may be readily designed even in the semiconductor memory device having a complicated command combination. Consequently, it is able to facilitate the verification of the design.
摘要翻译：提供给预定端子的信号被多次接受为命令，每次基于该命令并且根据变窄的操作模式控制内部电路，操作模式的数量依次变窄。由于多次接受确定操作模式所需的信息，因此可以减少输入命令所需的终端数量。特别地，在专用端子输入命令的情况下，不再需要其输入焊盘，输入电路等，从而可以减小芯片尺寸。通过减少端子数量来实现减少，这限制了封装尺寸。包括具有多个接受电路的指令控制电路。每个接收电路分别接收每次多次提供的信号。换句话说，根据信号补充的定时，分别操作不同的接受电路，并且控制内部电路。因此，即使在具有复杂的指令组合的半导体存储器件中，也可以容易地设计指令控制电路。因此，它能够方便验证设计。

10. 发明授权

US06535950B1 Semiconductor memory device having a refresh operation 有权
标题翻译：具有刷新操作的半导体存储器件
公开(公告)号：US06535950B1
公开(公告)日：2003-03-18
申请号：US09536988
申请日：2000-03-29
申请人： Akihiro Funyu , Shinya Fujioka , Hitoshi Ikeda , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato , Yasurou Matsuzaki
发明人： Akihiro Funyu , Shinya Fujioka , Hitoshi Ikeda , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato , Yasurou Matsuzaki
IPC分类号： G11C114093
CPC分类号： G11C7/1042 , G11C7/1063 , G11C7/20 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/4072
摘要： A semiconductor memory device, such as a DRAM, which needs to be refreshed for retaining data, is provided with a storing portion for storing data therein, and a busy signal outputting portion outputting a busy signal during the refresh operation.
摘要翻译：为了保存数据而需要刷新的诸如DRAM的半导体存储器件提供有用于存储数据的存储部分和在刷新操作期间输出忙信号的忙信号输出部分。

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