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1. 发明授权

US4656607A Electrically erasable programmable RAM 失效
标题翻译：电可擦除可编程RAM
公开(公告)号：US4656607A
公开(公告)日：1987-04-07
申请号：US632317
申请日：1984-07-19
申请人： Takaaki Hagiwara , Toru Kaga , Hiroo Masuda
发明人： Takaaki Hagiwara , Toru Kaga , Hiroo Masuda
IPC分类号： H01L27/112 , G11C11/40 , G11C11/404 , G11C14/00 , G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7881 , G11C11/404 , G11C16/0408
摘要： In a semiconductor memory made up of semiconductor memory elements, each consisting of a transistor of an MOS structure which has a charge-storage layer and which is formed on a semiconductor substrate, the improvement wherein a switching element is provided so that positive or negative charge can be stored or discharged from the charge-storage layer in a mode for writing data, and the charge-storage layer can be allowed to float electrically when in a mode for reading data.
摘要翻译：在由半导体存储元件构成的半导体存储器中，每个由具有电荷存储层的MOS结构的晶体管构成，并形成在半导体衬底上，其特征在于，提供一种开关元件，使得正或负电荷可以以用于写入数据的模式从电荷存储层存储或放电，并且当处于读取数据的模式时，可以允许电荷存储层电浮动。

2. 发明授权

US5119332A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5119332A
公开(公告)日：1992-06-02
申请号：US515345
申请日：1990-04-30
申请人： Katsuhiro Shimohigashi , Hiroo Masuda , Hiroshi Kawamoto
发明人： Katsuhiro Shimohigashi , Hiroo Masuda , Hiroshi Kawamoto
IPC分类号： G11C11/409 , G11C11/4091 , G11C11/4096 , G11C11/4097 , H01L23/522 , H01L27/108
CPC分类号： H01L27/108 , G11C11/409 , G11C11/4091 , G11C11/4096 , G11C11/4097 , H01L23/522 , H01L27/10805 , H01L2924/0002 , H01L2924/3011
摘要： A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed to a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.
摘要翻译：单元存储单元型的动态RAM集成电路设置有多条数据线，读出放大器，以与数据线相交的方式设置的多条字线，以及设置在数据线上的存储单元数据线与字线之间的交点。 RAM包括P型半导体衬底和形成在衬底中的N型阱区。存储单元设置在阱内，并且连接到日期线的读出放大器被构造成形成在半导体衬底中的一对N沟道MOSFET和形成在阱区中的一对P沟道MOSFET 。

3. 发明授权

US4539658A Semiconductor memory 失效
公开(公告)号：US4539658A
公开(公告)日：1985-09-03
申请号：US638982
申请日：1984-08-08
申请人： Katsuhiro Shimohigashi , Hiroo Masuda , Kunihiko Ikuzaki , Hiroshi Kawamoto
发明人： Katsuhiro Shimohigashi , Hiroo Masuda , Kunihiko Ikuzaki , Hiroshi Kawamoto
IPC分类号： G11C11/419 , G11C11/409 , G11C11/4091 , G11C11/4096 , G11C11/4097 , H01L21/822 , H01L21/8238 , H01L21/8242 , H01L23/522 , H01L27/04 , H01L27/092 , H01L27/10 , H01L27/108 , G11C11/40 , H01L29/78
CPC分类号： G11C11/409 , G11C11/4091 , G11C11/4096 , G11C11/4097 , H01L23/522 , H01L27/108 , H01L27/10805 , H01L2924/0002 , H01L2924/3011 , Y10S148/164
摘要： A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

4. 发明授权

US4455495A Programmable semiconductor integrated circuitry including a programming semiconductor element 失效
标题翻译：包括编程半导体元件的可编程半导体集成电路
公开(公告)号：US4455495A
公开(公告)日：1984-06-19
申请号：US192869
申请日：1980-10-01
申请人： Toshiaki Masuhara , Osamu Minato , Katsuhiro Shimohigashi , Hiroo Masuda , Hideo Sunami , Yoshio Sakai , Yoshiaki Kamigaki , Eiji Takeda , Yoshimune Hagiwara
发明人： Toshiaki Masuhara , Osamu Minato , Katsuhiro Shimohigashi , Hiroo Masuda , Hideo Sunami , Yoshio Sakai , Yoshiaki Kamigaki , Eiji Takeda , Yoshimune Hagiwara
IPC分类号： G11C8/10 , G11C17/16 , G11C17/18 , G11C29/00 , H01L21/263 , H01L21/268 , H01L21/768 , H01L23/525 , H01L27/10 , H01L27/04 , H01L29/04
CPC分类号： G11C29/785 , G11C17/16 , G11C17/18 , G11C8/10 , H01L21/2636 , H01L21/268 , H01L21/76894 , H01L23/5254 , H01L27/10 , H01L2924/0002
摘要： A programmable semiconductor integrated circuitry including a circuit programming element is disclosed. The circuit programming element can be activated in a short-circuit mode by the irradiation of a laser or electron beam or by ion implantation so that it is converted from its original nonconductive state into a conductive or conductable state, thereby providing electrical connection between circuits and/or circuit elements of the integrated circuitry for a desired circuit programming such as circuit creation, circuit conversion or circuit substitution.
摘要翻译：公开了一种包括电路编程元件的可编程半导体集成电路。电路编程元件可以通过激光或电子束的照射或通过离子注入在短路模式中被激活，使得其从其原始的非导通状态转换为导电或导电状态，由此提供电路之间的电连接 /或集成电路的电路元件，用于所需的电路编程，例如电路创建，电路转换或电路替换。

5. 发明授权

US06949387B2 Method of designing a semiconductor device 失效
标题翻译：设计半导体器件的方法
公开(公告)号：US06949387B2
公开(公告)日：2005-09-27
申请号：US10626718
申请日：2003-07-25
申请人： Hideo Miura , Makoto Ogasawara , Hiroo Masuda , Jun Murata , Noriaki Okamoto
发明人： Hideo Miura , Makoto Ogasawara , Hiroo Masuda , Jun Murata , Noriaki Okamoto
IPC分类号： H01L21/762 , H01L27/08 , H01L21/66
CPC分类号： H01L21/76205 , H01L21/76202 , H01L27/0802
摘要： A technique for a semiconductor device is provided that includes forming circuit regions on a device formation region and device isolation regions on a semiconductor substrate, a ratio of the width of a device isolation region to the width of adjacent circuit regions thereto is set at 2 to 50. A design method is also provided and includes conducting measurements such as of thicknesses of a pad oxide film and a nitride film, the internal stress of the nitride film, the width of both device formation and isolation regions, the depth of the etched portion of the nitride film for forming the groove in a device isolation region, conducting stress analysis in the proximity of the groove due to thermal oxidation, and setting values pertaining to the width of the device formation region and of the device isolation region which do not lead to occurrence of dislocation.
摘要翻译：提供了一种半导体器件的技术，其包括在器件形成区域上形成电路区域和半导体衬底上的器件隔离区域，器件隔离区域的宽度与其相邻电路区域的宽度的比率被设置为2至还提供了一种设计方法，包括进行测量，例如衬垫氧化膜和氮化物膜的厚度，氮化物膜的内部应力，器件形成和隔离区域的宽度，蚀刻部分的深度的用于在器件隔离区域中形成沟槽的氮化物膜，由于热氧化而在沟槽附近进行导电应力分析，以及与器件形成区域的宽度和不引导的器件隔离区域的设定值发生脱位。

6. 发明授权

US5889312A Semiconductor device having circuit element in stress gradient region by film for isolation and method of manufacturing the same 失效
标题翻译：具有用于隔离膜的应力梯度区域中的电路元件的半导体器件及其制造方法
公开(公告)号：US5889312A
公开(公告)日：1999-03-30
申请号：US890997
申请日：1997-07-10
申请人： Hideo Miura , Yasunobu Tanizaki , Eiji Wakimoto , Shinji Sakata , Makoto Ogasawara , Hiroo Masuda , Jun Murata , Noriaki Okamoto
发明人： Hideo Miura , Yasunobu Tanizaki , Eiji Wakimoto , Shinji Sakata , Makoto Ogasawara , Hiroo Masuda , Jun Murata , Noriaki Okamoto
IPC分类号： H01L21/762 , H01L27/08 , H01L3/22 , H01L21/265
CPC分类号： H01L21/76202 , H01L27/0802
摘要： A semiconductor device includes a thermal oxide film for isolation, a semiconductor region that becomes an element forming region with the circumference thereof surrounded by the oxide film and diffused resistance layers in the semiconductor region and provides a structure for controlling resistance value variation of diffused resistors originated in a stress generated at time of forming the oxide film for isolation. A distance between an end portion on a longer side closest to a thermal oxide film of the diffused layer and an end of the thermal oxide film is apart from each other by a predetermined value determined by stress distribution in the semiconductor region or by at least 4 .mu.m or more, the longitudinal direction of the diffused layer portion formed from the end of the thermal oxide film over to a stress distribution (gradient) forming region in the semiconductor region is parallel to the forming direction of the stress gradient, and resistance value distribution is formed parallel to the stress gradient in the diffused layer formed from the end of the thermal oxide film over to the stress distribution forming region in the semiconductor region.
摘要翻译：半导体器件包括用于隔离的热氧化膜，半导体区域，其成为元件形成区域，其周边被半导体区域中的氧化物膜和扩散电阻层包围，并且提供用于控制起始的扩散电阻器的电阻值变化的结构在形成用于隔离的氧化膜时产生的应力。最靠近扩散层的热氧化膜的较长侧的端部与热氧化膜的端部之间的距离彼此分开由半导体区域中的应力分布确定的预定值或至少4 从热氧化膜的端部到半导体区域的应力分布（梯度）形成区域形成的扩散层部的纵向方向平行于应力梯度的形成方向，电阻值分布形成为平行于从热氧化膜的端部到半导体区域中的应力分布形成区域形成的扩散层中的应力梯度。

7. 发明授权

US5448520A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5448520A
公开(公告)日：1995-09-05
申请号：US306612
申请日：1994-09-15
申请人： Katsuhiro Shimohigashi , Hiroo Masuda , Kunihiko Ikuzaki , Hiroshi Kawamoto
发明人： Katsuhiro Shimohigashi , Hiroo Masuda , Kunihiko Ikuzaki , Hiroshi Kawamoto
IPC分类号： G11C11/409 , G11C11/4091 , G11C11/4096 , G11C11/4097 , H01L23/522 , H01L27/108 , G11C13/00
CPC分类号： G11C11/409 , G11C11/4091 , G11C11/4096 , G11C11/4097 , H01L23/522 , H01L27/108 , H01L27/10805 , H01L2924/0002 , H01L2924/3011
摘要： A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed irk the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.
摘要翻译：单元存储单元型的动态RAM集成电路设置有多条数据线，读出放大器，以与数据线相交的方式设置的多条字线，以及设置在数据线上的存储单元数据线与字线之间的交点。 RAM包括P型半导体衬底和与衬底形成的N型阱区。存储单元设置在阱内，并且连接到日期线的读出放大器由形成在半导体衬底中的一对N沟道MOSFET和形成在阱区中的一对P沟道MOSFET构成。

8. 发明授权

US06337517B1 Semiconductor device and method of fabricating same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06337517B1
公开(公告)日：2002-01-08
申请号：US09151590
申请日：1998-09-11
申请人： Hiroyuki Ohta , Hideo Miura , Kazushige Sato , Takeshi Kimura , Hiroo Masuda
发明人： Hiroyuki Ohta , Hideo Miura , Kazushige Sato , Takeshi Kimura , Hiroo Masuda
IPC分类号： H01L2348
CPC分类号： H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device capable of operating at a high speed or of having many functions. In this device, delamination of buried electrodes is prevented and thus high reliability is offered. The depth A of contact holes, the minimum linewidth R of a lower metallization layer, and the thickness B of the lower metallization layer satisfy relations given by (0.605/R)0.5
摘要翻译：能够高速运转或具有许多功能的半导体装置。在该装置中，防止了埋入电极的分层，从而提供了高可靠性。接触孔的深度A，下部金属化层的最小线宽R和下部金属化层的厚度B满足关系式

9. 发明授权

US5689457A Semiconductor Memory 失效
标题翻译：半导体存储器
公开(公告)号：US5689457A
公开(公告)日：1997-11-18
申请号：US611636
申请日：1996-03-06
申请人： Katsuhiro Shimohigashi , Hiroo Masuda , Kunihiko Ikuzaki , Hiroshi Kawamoto
发明人： Katsuhiro Shimohigashi , Hiroo Masuda , Kunihiko Ikuzaki , Hiroshi Kawamoto
IPC分类号： G11C7/10 , G11C11/409 , G11C11/4091 , G11C11/4096 , G11C11/4097 , H01L23/522 , H01L27/108 , G11C13/00
CPC分类号： G11C7/1048 , G11C11/409 , G11C11/4091 , G11C11/4096 , G11C11/4097 , H01L23/522 , H01L27/108 , H01L27/10805 , H01L2924/0002 , H01L2924/3011
摘要： A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.
摘要翻译：单元存储单元型的动态RAM集成电路设置有多条数据线，读出放大器，以与数据线相交的方式设置的多条字线，以及设置在数据线上的存储单元数据线与字线之间的交点。 RAM包括P型半导体衬底和形成在衬底中的N型阱区。存储单元设置在阱内，并且连接到日期线的读出放大器由形成在半导体衬底中的一对N沟道MOSFET和形成在阱区中的一对P沟道MOSFET构成。

10. 发明授权

US5170374A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5170374A
公开(公告)日：1992-12-08
申请号：US864934
申请日：1992-04-07
申请人： Katsuhiro Shimohigashi , Hiroo Masuda , Kunihiko Ikuzaki
发明人： Katsuhiro Shimohigashi , Hiroo Masuda , Kunihiko Ikuzaki
IPC分类号： G11C11/409 , G11C11/4091 , G11C11/4096 , G11C11/4097 , H01L23/522 , H01L27/108
CPC分类号： H01L27/10805 , G11C11/409 , G11C11/4091 , G11C11/4096 , G11C11/4097 , H01L23/522 , H01L27/108 , H01L2924/0002 , H01L2924/3011
摘要： A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.
摘要翻译：单元存储单元型的动态RAM集成电路设置有多条数据线，读出放大器，以与数据线相交的方式设置的多条字线，以及设置在数据线上的存储单元数据线与字线之间的交点。 RAM包括P型半导体衬底和形成在衬底中的N型阱区。存储单元设置在阱内，并且连接到日期线的读出放大器由形成在半导体衬底中的一对N沟道MOSFET和形成在阱区中的一对P沟道MOSFET构成。

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