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1. 发明授权

US07368761B1 Electrostatic discharge protection device and fabrication method thereof 有权
标题翻译：静电放电保护装置及其制造方法
公开(公告)号：US07368761B1
公开(公告)日：2008-05-06
申请号：US11683753
申请日：2007-03-08
申请人： Tai-Hsiang Lai , Wei-Jen Chang , Ming-Dou Ker , Tien-Hao Tang
发明人： Tai-Hsiang Lai , Wei-Jen Chang , Ming-Dou Ker , Tien-Hao Tang
IPC分类号： H01L31/111 , H01L21/328
CPC分类号： H01L27/0262
摘要： An electrostatic discharge (ESD) protection device and a fabrication method thereof are provided. The ESD protection device with an embedded high-voltage P type SCR (EHVPSCR) structure of the present invention is employed to guide the ESD current/voltage to a system voltage trace VDD via a pad.
摘要翻译：提供一种静电放电（ESD）保护装置及其制造方法。采用本发明的具有嵌入式高压P型SCR（EHVPSCR）结构的ESD保护装置，通过焊盘将ESD电流/电压引导到系统电压迹线VDD。

2. 发明授权

US07655980B1 Device for ESD protection circuit 有权
标题翻译： ESD保护电路装置
公开(公告)号：US07655980B1
公开(公告)日：2010-02-02
申请号：US12178058
申请日：2008-07-23
申请人： Mei-Ling Chao , Chia-Yun Chen , Tai-Hsiang Lai , Tien-Hao Tang
发明人： Mei-Ling Chao , Chia-Yun Chen , Tai-Hsiang Lai , Tien-Hao Tang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/0847 , H01L27/0266 , H01L29/0626 , H01L29/0878 , H01L29/4238 , H01L29/7816
摘要： A LDNMOS device for an ESD protection circuit including a P-type substrate and an N-type deep well region is provided. The P-type substrate includes a first area and a second area. The N-type deep well region is in the first and second areas of the P-type substrate. The LDNMOS device further includes a gate electrode disposed on the P-type substrate between the first and second areas, a P-type implanted region disposed in the first area of the P-type substrate, an N-type grade region disposed in the N-type deep well region of the first area, an N-type first doped region disposed in the N-type grade region, a P-type body region disposed in the N-type deep well region of the second area, an N-type second doped region disposed in the P-type body region, and a P-type doped region disposed in the P-type body region and adjacent to the N-type second doped region.
摘要翻译：提供一种用于包括P型衬底和N型深阱区的ESD保护电路的LDNMOS器件。 P型基板包括第一区域和第二区域。 N型深井区域位于P型基板的第一和第二区域中。 LDNMOS器件还包括设置在第一和第二区域之间的P型衬底上的栅电极，设置在P型衬底的第一区域中的P型注入区域，设置在N型衬底中的N型等级区域第一区域的深井区域，设置在N型等级区域中的N型第一掺杂区域，设置在第二区域的N型深阱区域中的P型体区域，N型第二掺杂区域设置在P型体区域中，P型掺杂区域设置在P型体区域中且与N型第二掺杂区域相邻。

3. 发明授权

US08723263B2 Electrostatic discharge protection device 有权
标题翻译：静电放电保护装置
公开(公告)号：US08723263B2
公开(公告)日：2014-05-13
申请号：US13556219
申请日：2012-07-24
申请人： Mei-Ling Chao , Yi-Chun Chen , Lu-An Chen , Tai-Hsiang Lai , Tien-Hao Tang
发明人： Mei-Ling Chao , Yi-Chun Chen , Lu-An Chen , Tai-Hsiang Lai , Tien-Hao Tang
IPC分类号： H01L23/62
CPC分类号： H01L27/027 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) includes a semiconductor substrate having the first conductive type, a well having the first conductive type, a buried layer having the second conductive type and a well having the second conductive type. The buried layer having a second conductive type is disposed in the semiconductor substrate under the well having the first conductive type. The well having the second conductive type disposed to divide the well having the first conductive type into a first well and a second well. The well having the second conductive type contacts the buried layer, and the well having the second conductive type and the buried layer are jointly used to isolate the first well from the second well.
摘要翻译：静电放电（ESD）包括具有第一导电类型的半导体衬底，具有第一导电类型的阱，具有第二导电类型的掩埋层和具有第二导电类型的阱。具有第二导电类型的掩埋层在具有第一导电类型的阱下面设置在半导体衬底中。具有第二导电类型的阱被设置成将具有第一导电类型的阱分成第一阱和第二阱。具有第二导电类型的阱接触掩埋层，并且具有第二导电类型和掩埋层的阱共同用于将第一阱与第二阱隔离。

4. 发明授权

US08507981B2 Method of manufacturing NMOS transistor with low trigger voltage 有权
标题翻译：具有低触发电压的NMOS晶体管的制造方法
公开(公告)号：US08507981B2
公开(公告)日：2013-08-13
申请号：US13271239
申请日：2011-10-12
申请人： Lu-An Chen , Tai-Hsiang Lai , Tien-Hao Tang
发明人： Lu-An Chen , Tai-Hsiang Lai , Tien-Hao Tang
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L29/41758 , H01L27/0277 , H01L29/0696 , H01L29/1087 , H01L29/42368 , H01L29/7816
摘要： A method for forming an NMOS transistor includes forming a P-substrate; forming an N-well on the P-substrate; forming an N-drift region on the N-well; forming an n+ drain on the N-drift region; forming a plurality of first contacts on the n+ drain along a longitudinal direction; forming a P-body on the N-well; forming a source on the P-body, the source including a plurality of n+ doped regions and at least one p+ doped region arranged along the longitudinal direction; forming a plurality of second contacts on the plurality of n+ doped regions and the at least one p+ doped region; forming a polygate on the P-body; and forming a gate oxide between the polygate and the source.
摘要翻译：一种形成NMOS晶体管的方法包括：形成P基片; 在P基板上形成N阱; 在N阱上形成N漂移区; 在N漂移区上形成n +漏极; 在所述n +漏极上沿纵向方向形成多个第一触点; 在N阱上形成P体; 在所述P体上形成源极，所述源极包括多个n +掺杂区域和沿着所述纵向排列的至少一个p +掺杂区域; 在所述多个n +掺杂区域和所述至少一个p +掺杂区域上形成多个第二接触; 在P体上形成多孔盖; 以及在所述多晶硅栅极和所述源极之间形成栅极氧化物。

5. 发明申请

US20140027856A1 ELECTROSTATIC DISCHARGE PROTECTION DEVICE 有权
标题翻译：静电放电保护装置
公开(公告)号：US20140027856A1
公开(公告)日：2014-01-30
申请号：US13556219
申请日：2012-07-24
申请人： Mei-Ling Chao , Yi-Chun Chen , Lu-An Chen , Tai-Hsiang Lai , Tien-Hao Tang
发明人： Mei-Ling Chao , Yi-Chun Chen , Lu-An Chen , Tai-Hsiang Lai , Tien-Hao Tang
IPC分类号： H01L27/06
CPC分类号： H01L27/027 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) includes a semiconductor substrate having the first conductive type, a well having the first conductive type, a buried layer having the second conductive type and a well having the second conductive type. The buried layer having a second conductive type is disposed in the semiconductor substrate under the well having the first conductive type. The well having the second conductive type disposed to divide the well having the first conductive type into a first well and a second well. The well having the second conductive type contacts the buried layer, and the well having the second conductive type and the buried layer are jointly used to isolate the first well from the second well.
摘要翻译：静电放电（ESD）包括具有第一导电类型的半导体衬底，具有第一导电类型的阱，具有第二导电类型的掩埋层和具有第二导电类型的阱。具有第二导电类型的掩埋层在具有第一导电类型的阱下面设置在半导体衬底中。具有第二导电类型的阱被设置成将具有第一导电类型的阱分成第一阱和第二阱。具有第二导电类型的阱接触掩埋层，并且具有第二导电类型和掩埋层的阱共同用于将第一阱与第二阱隔离。

6. 发明授权

US08530969B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08530969B2
公开(公告)日：2013-09-10
申请号：US13369423
申请日：2012-02-09
申请人： Lu-An Chen , Tai-Hsiang Lai , Tien-Hao Tang
发明人： Lu-An Chen , Tai-Hsiang Lai , Tien-Hao Tang
IPC分类号： H01L23/62
CPC分类号： H01L29/7835 , H01L27/0251
摘要： A semiconductor device includes a substrate, a gate structure, a source structure and a drain structure. The substrate includes a deep well region, and the gate structure is disposed on the deep well region. The source structure is formed within the deep well and located at a first side of the gate structure. The drain structure is formed within the deep well region and located at a second side of the gate structure. The drain structure includes a first doped region of a first conductivity type, a first electrode and a second doped region of a second conductivity type. The first doped region is located in the deep well region; the first electrode is electrically connected to the first doped region. The second doped region is disposed within the first doped region and between the first electrode and the gate structure.
摘要翻译：半导体器件包括衬底，栅极结构，源极结构和漏极结构。衬底包括深阱区，并且栅极结构设置在深阱区上。源结构形成在深阱内并且位于栅极结构的第一侧。漏极结构形成在深阱区域内，并且位于栅极结构的第二侧。漏极结构包括第一导电类型的第一掺杂区域，第二导电类型的第一电极和第二掺杂区域。第一掺杂区位于深井区; 第一电极电连接到第一掺杂区域。第二掺杂区域设置在第一掺杂区域内并且位于第一电极和栅极结构之间。

7. 发明申请

US20130181211A1 METAL OXIDE SEMICONDUCTOR DEVICE 有权
标题翻译：金属氧化物半导体器件
公开(公告)号：US20130181211A1
公开(公告)日：2013-07-18
申请号：US13353235
申请日：2012-01-18
申请人： Lu-An Chen , Chang-Tzu Wang , Tai-Hsiang Lai , Tien-Hao Tang
发明人： Lu-An Chen , Chang-Tzu Wang , Tai-Hsiang Lai , Tien-Hao Tang
IPC分类号： H01L29/12
CPC分类号： H01L27/0262 , H01L29/0692 , H01L29/10 , H01L29/87
摘要： Provided is a metal oxide semiconductor device, including a substrate, a gate, a first-type first heavily doped region, a first-type drift region, a second-type first heavily doped region, a contact, a first electrode, and a second electrode. The gate is disposed on the substrate. The first-type first heavily doped region is disposed in the substrate at a side of the gate. The first-type drift region is disposed in the substrate at another side of the gate. The second-type first heavily doped region is disposed in the first-type drift region. The contact is electrically connected to the second-type first heavily doped region. The contact is the closest contact to the gate on the first-type drift region. The first electrode is electrically connected to the contact, and the second electrode is electrically connected to the first-type first heavily doped region and the gate.
摘要翻译：提供了一种金属氧化物半导体器件，其包括衬底，栅极，第一类型的第一重掺杂区域，第一类型漂移区域，第二类型第一重掺杂区域，接触区，第一电极和第二电极。栅极设置在基板上。第一类型的第一重掺杂区域设置在栅极侧的衬底中。第一类型漂移区域设置在栅极另一侧的衬底中。第二类型的第一重掺杂区域设置在第一类漂移区域中。触点电连接到第二类型的第一重掺杂区域。触点是与第一型漂移区上的栅极最接近的接触点。第一电极电连接到触点，并且第二电极电连接到第一类型的第一重掺杂区域和栅极。

8. 发明授权

US08477467B2 Electrostatic discharge protection circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US08477467B2
公开(公告)日：2013-07-02
申请号：US13190578
申请日：2011-07-26
申请人： Lu-An Chen , Tai-Hsiang Lai , Tien-Hao Tang
发明人： Lu-An Chen , Tai-Hsiang Lai , Tien-Hao Tang
IPC分类号： H02H3/22
CPC分类号： H02H9/046
摘要： An electrostatic discharge protection circuit is located between a first voltage terminal and a second voltage terminal. The electrostatic discharge protection circuit includes a first semiconductor switch and a second semiconductor switch. The first semiconductor switch is electrically connected to the first voltage terminal. If a voltage at the first voltage terminal complies with a starting condition, the first semiconductor switch is turned on, so that an electrostatic discharge current flows through the first voltage terminal and the first semiconductor switch. The second semiconductor switch is electrically connected between the first semiconductor switch and the second voltage terminal, wherein the electrostatic discharge current from the first semiconductor switch passes to the second voltage terminal through the second semiconductor switch.
摘要翻译：静电放电保护电路位于第一电压端子和第二电压端子之间。静电放电保护电路包括第一半导体开关和第二半导体开关。第一半导体开关电连接到第一电压端子。如果第一电压端子处的电压符合启动条件，则第一半导体开关导通，使得静电放电电流流过第一电压端子和第一半导体开关。第二半导体开关电连接在第一半导体开关和第二电压端子之间，其中来自第一半导体开关的静电放电电流通过第二半导体开关传递到第二电压端子。

9. 发明申请

US20110042716A1 ESD protection device structure 有权
标题翻译： ESD保护器件结构
公开(公告)号：US20110042716A1
公开(公告)日：2011-02-24
申请号：US12544225
申请日：2009-08-20
申请人： Tai-Hsiang Lai , Kuei-Chih Fan , Tien-Hao Tang
发明人： Tai-Hsiang Lai , Kuei-Chih Fan , Tien-Hao Tang
IPC分类号： H01L29/73 , H01L27/102
CPC分类号： H01L27/0266
摘要： An ESD protection device structure includes a well having a first conductive type, a first doped region having a second conductive type disposed in the well, a second doped region having the first conductive type, and a third doped region having the second conductive type disposed in the well. The second doped region is disposed within the first doped region so as to form a vertical BJT, and the first doped region, the well and the third doped region forms a lateral BJT, so that pulse voltage that the ESD protection structure can tolerate can be raised.
摘要翻译： ESD保护器件结构包括具有第一导电类型的阱，设置在阱中的具有第二导电类型的第一掺杂区，具有第一导电类型的第二掺杂区和具有第二导电类型的第三掺杂区，那个井第二掺杂区域设置在第一掺杂区域内以形成垂直BJT，并且第一掺杂区域，阱和第三掺杂区域形成横向BJT，使得ESD保护结构可以容忍的脉冲电压可以是上调。

10. 发明授权

US08716801B2 Metal oxide semiconductor device 有权
标题翻译：金属氧化物半导体器件
公开(公告)号：US08716801B2
公开(公告)日：2014-05-06
申请号：US13353235
申请日：2012-01-18
申请人： Lu-An Chen , Chang-Tzu Wang , Tai-Hsiang Lai , Tien-Hao Tang
发明人： Lu-An Chen , Chang-Tzu Wang , Tai-Hsiang Lai , Tien-Hao Tang
IPC分类号： H01L23/62
CPC分类号： H01L27/0262 , H01L29/0692 , H01L29/10 , H01L29/87
摘要： Provided is a metal oxide semiconductor device, including a substrate, a gate, a first-type first heavily doped region, a first-type drift region, a second-type first heavily doped region, a contact, a first electrode, and a second electrode. The gate is disposed on the substrate. The first-type first heavily doped region is disposed in the substrate at a side of the gate. The first-type drift region is disposed in the substrate at another side of the gate. The second-type first heavily doped region is disposed in the first-type drift region. The contact is electrically connected to the second-type first heavily doped region. The contact is the closest contact to the gate on the first-type drift region. The first electrode is electrically connected to the contact, and the second electrode is electrically connected to the first-type first heavily doped region and the gate.
摘要翻译：提供了一种金属氧化物半导体器件，其包括衬底，栅极，第一类型的第一重掺杂区域，第一类型漂移区域，第二类型第一重掺杂区域，接触区，第一电极和第二电极。栅极设置在基板上。第一类型的第一重掺杂区域设置在栅极侧的衬底中。第一类漂移区域设置在栅极另一侧的衬底中。第二类型的第一重掺杂区域设置在第一类漂移区域中。触点电连接到第二类型的第一重掺杂区域。触点是与第一型漂移区上的栅极最接近的接触点。第一电极电连接到触点，并且第二电极电连接到第一类型的第一重掺杂区域和栅极。

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