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1. 发明授权

US07655980B1 Device for ESD protection circuit 有权
标题翻译： ESD保护电路装置
公开(公告)号：US07655980B1
公开(公告)日：2010-02-02
申请号：US12178058
申请日：2008-07-23
申请人： Mei-Ling Chao , Chia-Yun Chen , Tai-Hsiang Lai , Tien-Hao Tang
发明人： Mei-Ling Chao , Chia-Yun Chen , Tai-Hsiang Lai , Tien-Hao Tang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/0847 , H01L27/0266 , H01L29/0626 , H01L29/0878 , H01L29/4238 , H01L29/7816
摘要： A LDNMOS device for an ESD protection circuit including a P-type substrate and an N-type deep well region is provided. The P-type substrate includes a first area and a second area. The N-type deep well region is in the first and second areas of the P-type substrate. The LDNMOS device further includes a gate electrode disposed on the P-type substrate between the first and second areas, a P-type implanted region disposed in the first area of the P-type substrate, an N-type grade region disposed in the N-type deep well region of the first area, an N-type first doped region disposed in the N-type grade region, a P-type body region disposed in the N-type deep well region of the second area, an N-type second doped region disposed in the P-type body region, and a P-type doped region disposed in the P-type body region and adjacent to the N-type second doped region.
摘要翻译：提供一种用于包括P型衬底和N型深阱区的ESD保护电路的LDNMOS器件。 P型基板包括第一区域和第二区域。 N型深井区域位于P型基板的第一和第二区域中。 LDNMOS器件还包括设置在第一和第二区域之间的P型衬底上的栅电极，设置在P型衬底的第一区域中的P型注入区域，设置在N型衬底中的N型等级区域第一区域的深井区域，设置在N型等级区域中的N型第一掺杂区域，设置在第二区域的N型深阱区域中的P型体区域，N型第二掺杂区域设置在P型体区域中，P型掺杂区域设置在P型体区域中且与N型第二掺杂区域相邻。

2. 发明申请

US20100019318A1 DEVICE FOR ESD PROTECTION CIRCUIT 有权
标题翻译： ESD保护电路装置
公开(公告)号：US20100019318A1
公开(公告)日：2010-01-28
申请号：US12178058
申请日：2008-07-23
申请人： Mei-Ling Chao , Chia-Yun Chen , Tai-Hsiang Lai , Tien-Hao Tang
发明人： Mei-Ling Chao , Chia-Yun Chen , Tai-Hsiang Lai , Tien-Hao Tang
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L29/0847 , H01L27/0266 , H01L29/0626 , H01L29/0878 , H01L29/4238 , H01L29/7816
摘要： A LDNMOS device for an ESD protection circuit including a P-type substrate and an N-type deep well region is provided. The P-type substrate includes a first area and a second area. The N-type deep well region is in the first and second areas of the P-type substrate. The LDNMOS device further includes a gate electrode disposed on the P-type substrate between the first and second areas, a P-type implanted region disposed in the first area of the P-type substrate, an N-type grade region disposed in the N-type deep well region of the first area, an N-type first doped region disposed in the N-type grade region, a P-type body region disposed in the N-type deep well region of the second area, an N-type second doped region disposed in the P-type body region, and a P-type doped region disposed in the P-type body region and adjacent to the N-type second doped region.
摘要翻译：提供一种用于包括P型衬底和N型深阱区的ESD保护电路的LDNMOS器件。 P型基板包括第一区域和第二区域。 N型深井区域位于P型基板的第一和第二区域中。 LDNMOS器件还包括设置在第一和第二区域之间的P型衬底上的栅电极，设置在P型衬底的第一区域中的P型注入区域，设置在N型衬底中的N型等级区域第一区域的深井区域，设置在N型等级区域中的N型第一掺杂区域，设置在第二区域的N型深阱区域中的P型体区域，N型第二掺杂区域设置在P型体区域中，P型掺杂区域设置在P型体区域中且与N型第二掺杂区域相邻。

3. 发明申请

US20140027856A1 ELECTROSTATIC DISCHARGE PROTECTION DEVICE 有权
标题翻译：静电放电保护装置
公开(公告)号：US20140027856A1
公开(公告)日：2014-01-30
申请号：US13556219
申请日：2012-07-24
申请人： Mei-Ling Chao , Yi-Chun Chen , Lu-An Chen , Tai-Hsiang Lai , Tien-Hao Tang
发明人： Mei-Ling Chao , Yi-Chun Chen , Lu-An Chen , Tai-Hsiang Lai , Tien-Hao Tang
IPC分类号： H01L27/06
CPC分类号： H01L27/027 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) includes a semiconductor substrate having the first conductive type, a well having the first conductive type, a buried layer having the second conductive type and a well having the second conductive type. The buried layer having a second conductive type is disposed in the semiconductor substrate under the well having the first conductive type. The well having the second conductive type disposed to divide the well having the first conductive type into a first well and a second well. The well having the second conductive type contacts the buried layer, and the well having the second conductive type and the buried layer are jointly used to isolate the first well from the second well.
摘要翻译：静电放电（ESD）包括具有第一导电类型的半导体衬底，具有第一导电类型的阱，具有第二导电类型的掩埋层和具有第二导电类型的阱。具有第二导电类型的掩埋层在具有第一导电类型的阱下面设置在半导体衬底中。具有第二导电类型的阱被设置成将具有第一导电类型的阱分成第一阱和第二阱。具有第二导电类型的阱接触掩埋层，并且具有第二导电类型和掩埋层的阱共同用于将第一阱与第二阱隔离。

4. 发明授权

US08723263B2 Electrostatic discharge protection device 有权
标题翻译：静电放电保护装置
公开(公告)号：US08723263B2
公开(公告)日：2014-05-13
申请号：US13556219
申请日：2012-07-24
申请人： Mei-Ling Chao , Yi-Chun Chen , Lu-An Chen , Tai-Hsiang Lai , Tien-Hao Tang
发明人： Mei-Ling Chao , Yi-Chun Chen , Lu-An Chen , Tai-Hsiang Lai , Tien-Hao Tang
IPC分类号： H01L23/62
CPC分类号： H01L27/027 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) includes a semiconductor substrate having the first conductive type, a well having the first conductive type, a buried layer having the second conductive type and a well having the second conductive type. The buried layer having a second conductive type is disposed in the semiconductor substrate under the well having the first conductive type. The well having the second conductive type disposed to divide the well having the first conductive type into a first well and a second well. The well having the second conductive type contacts the buried layer, and the well having the second conductive type and the buried layer are jointly used to isolate the first well from the second well.
摘要翻译：静电放电（ESD）包括具有第一导电类型的半导体衬底，具有第一导电类型的阱，具有第二导电类型的掩埋层和具有第二导电类型的阱。具有第二导电类型的掩埋层在具有第一导电类型的阱下面设置在半导体衬底中。具有第二导电类型的阱被设置成将具有第一导电类型的阱分成第一阱和第二阱。具有第二导电类型的阱接触掩埋层，并且具有第二导电类型和掩埋层的阱共同用于将第一阱与第二阱隔离。

5. 发明授权

US08604548B2 Semiconductor device having ESD device 有权
标题翻译：具有ESD器件的半导体器件
公开(公告)号：US08604548B2
公开(公告)日：2013-12-10
申请号：US13304086
申请日：2011-11-23
申请人： Chang-Tzu Wang , Mei-Ling Chao , Chien-Ting Lin
发明人： Chang-Tzu Wang , Mei-Ling Chao , Chien-Ting Lin
IPC分类号： H01L27/12
CPC分类号： H01L29/66795 , H01L21/26513 , H01L21/823821 , H01L27/0924
摘要： A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate of a first conductivity type, a fin, a gate, source and drain regions of a second conductivity type, and a first doped region of the second conductivity type. A plurality of isolation structures is formed on the substrate. The fin is disposed on the substrate between two adjacent isolation structures. The gate is disposed on the isolation structures and covers a portion of the fin, wherein the portion of the fin covered by the gate is of the first conductivity type. The source and drain regions is configured in the fin at respective sides of the gate. The first doped region is configured in the fin underlying the source and drain regions and adjoining the substrate. The first doped region has an impurity concentration lower than that of the source and drain regions.
摘要翻译：提供了一种半导体器件及其制造方法。半导体器件包括具有第二导电类型的第一导电类型，鳍状物，栅极，源极和漏极区域以及第二导电类型的第一掺杂区域的衬底。在基板上形成多个隔离结构。翅片设置在两个相邻隔离结构之间的基板上。栅极设置在隔离结构上并覆盖翅片的一部分，其中由栅极覆盖的鳍的部分是第一导电类型。源极和漏极区域在栅极的相应侧配置在鳍片中。第一掺杂区域配置在源极和漏极区域下方的鳍片中，并与衬底相邻。第一掺杂区的杂质浓度低于源区和漏区。

6. 发明授权

US07071575B2 Semiconductor chip capable of implementing wire bonding over active circuits 有权
标题翻译：能够在有源电路上实现引线键合的半导体芯片
公开(公告)号：US07071575B2
公开(公告)日：2006-07-04
申请号：US10904431
申请日：2004-11-10
申请人： Bing-Chang Wu , Kun-Chih Wang , Mei-Ling Chao , Shiao-Shien Chen
发明人： Bing-Chang Wu , Kun-Chih Wang , Mei-Ling Chao , Shiao-Shien Chen
IPC分类号： H01L23/12 , H00L23/48 , H00L29/40
CPC分类号： H01L24/05 , H01L23/53228 , H01L2224/02166 , H01L2224/05093 , H01L2224/05095 , H01L2224/05624 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/00014
摘要： A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor bottom.
摘要翻译：提供了能够通过有源电路（BOAC）实现引线键合的半导体芯片。该半导体芯片包括一个焊盘结构，该焊盘结构包括一个可粘合的金属焊盘，一个顶部互连金属层，一个应力缓冲电介质，以及至少一个可焊接的金属焊盘和顶部互连金属层之间的第一通孔塞。半导体芯片还包括至少互连金属层，互连金属层和焊盘结构之间的至少第二通孔插头以及位于半导体底部上的焊盘结构下方的有源电路。

7. 发明授权

US07372168B2 Semiconductor chip capable of implementing wire bonding over active circuits 有权
标题翻译：能够在有源电路上实现引线键合的半导体芯片
公开(公告)号：US07372168B2
公开(公告)日：2008-05-13
申请号：US11379572
申请日：2006-04-21
申请人： Bing-Chang Wu , Kun-Chih Wang , Mei-Ling Chao , Shiao-Shien Chen
发明人： Bing-Chang Wu , Kun-Chih Wang , Mei-Ling Chao , Shiao-Shien Chen
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L23/53228 , H01L2224/02166 , H01L2224/05093 , H01L2224/05095 , H01L2224/05624 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/00014
摘要： A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor substrate.
摘要翻译：提供了能够通过有源电路（BOAC）实现引线键合的半导体芯片。该半导体芯片包括一个焊盘结构，该焊盘结构包括一个可粘合的金属焊盘，一个顶部互连金属层，一个应力缓冲电介质，以及至少一个可焊接的金属焊盘和顶部互连金属层之间的第一通孔塞。半导体芯片还至少包括互连金属层，在互连金属层和焊盘结构之间的至少第二通孔插塞以及位于半导体衬底上的焊盘结构下方的有源电路。

8. 发明申请

US20060186545A1 SEMICONDUCTOR CHIP CAPABLE OF IMPLEMENTING WIRE BONDING OVER ACTIVE CIRCUITS 有权
标题翻译：在有源电路上实现线路连接的半导体芯片
公开(公告)号：US20060186545A1
公开(公告)日：2006-08-24
申请号：US11379572
申请日：2006-04-21
申请人： Bing-Chang Wu , Kun-Chih Wang , Mei-Ling Chao , Shiao-Shien Chen
发明人： Bing-Chang Wu , Kun-Chih Wang , Mei-Ling Chao , Shiao-Shien Chen
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L23/53228 , H01L2224/02166 , H01L2224/05093 , H01L2224/05095 , H01L2224/05624 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/00014
摘要： A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor substrate.
摘要翻译：提供了能够通过有源电路（BOAC）实现引线键合的半导体芯片。该半导体芯片包括一个焊盘结构，该焊盘结构包括一个可粘合的金属焊盘，一个顶部互连金属层，一个应力缓冲电介质，以及至少一个可焊接的金属焊盘与顶部互连金属层之间的第一通孔塞。半导体芯片还至少包括互连金属层，在互连金属层和焊盘结构之间的至少第二通孔插塞以及位于半导体衬底上的焊盘结构下方的有源电路。

9. 发明申请

US20130126972A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130126972A1
公开(公告)日：2013-05-23
申请号：US13304086
申请日：2011-11-23
申请人： Chang-Tzu Wang , Mei-Ling Chao , Chien-Ting Lin
发明人： Chang-Tzu Wang , Mei-Ling Chao , Chien-Ting Lin
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L29/66795 , H01L21/26513 , H01L21/823821 , H01L27/0924
摘要： A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate of a first conductivity type, a fin, a gate, source and drain regions of a second conductivity type, and a first doped region of the second conductivity type. A plurality of isolation structures is formed on the substrate. The fin is disposed on the substrate between two adjacent isolation structures. The gate is disposed on the isolation structures and covers a portion of the fin, wherein the portion of the fin covered by the gate is of the first conductivity type. The source and drain regions is configured in the fin at respective sides of the gate. The first doped region is configured in the fin underlying the source and drain regions and adjoining the substrate. The first doped region has an impurity concentration lower than that of the source and drain regions.
摘要翻译：提供了一种半导体器件及其制造方法。半导体器件包括具有第二导电类型的第一导电类型，鳍状物，栅极，源极和漏极区域以及第二导电类型的第一掺杂区域的衬底。在基板上形成多个隔离结构。翅片设置在两个相邻隔离结构之间的基板上。栅极设置在隔离结构上并覆盖翅片的一部分，其中由栅极覆盖的鳍的部分是第一导电类型。源极和漏极区域在栅极的相应侧配置在鳍片中。第一掺杂区域配置在源极和漏极区域下方的鳍片中，并与衬底相邻。第一掺杂区的杂质浓度低于源区和漏区。

10. 发明申请

US20060097406A1 SEMICONDUCTOR CHIP CAPABLE OF IMPLEMENTING WIRE BONDING OVER ACTIVE CIRCUITS 有权
标题翻译：在有源电路上实现线路连接的半导体芯片
公开(公告)号：US20060097406A1
公开(公告)日：2006-05-11
申请号：US10904431
申请日：2004-11-10
申请人： Bing-Chang Wu , Kun-Chih Wang , Mei-Ling Chao , Shiao-Shien Chen
发明人： Bing-Chang Wu , Kun-Chih Wang , Mei-Ling Chao , Shiao-Shien Chen
IPC分类号： H01L23/52 , H01L23/48
CPC分类号： H01L24/05 , H01L23/53228 , H01L2224/02166 , H01L2224/05093 , H01L2224/05095 , H01L2224/05624 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/00014
摘要： A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor bottom.
摘要翻译：提供了能够通过有源电路（BOAC）实现引线键合的半导体芯片。该半导体芯片包括一个焊盘结构，该焊盘结构包括一个可粘合的金属焊盘，一个顶部互连金属层，一个应力缓冲电介质，以及至少一个可焊接的金属焊盘和顶部互连金属层之间的第一通孔塞。半导体芯片还包括至少互连金属层，互连金属层和焊盘结构之间的至少第二通孔插头以及位于半导体底部上的焊盘结构下方的有源电路。

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