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1. 发明授权

US5801549A Simultaneous transmission bidirectional repeater and initialization mechanism 失效
标题翻译：同时传输双向中继器和初始化机制
公开(公告)号：US5801549A
公开(公告)日：1998-09-01
申请号：US766642
申请日：1996-12-13
申请人： Tai Anh Cao , Tom Tein-Cheng Chiu
发明人： Tai Anh Cao , Tom Tein-Cheng Chiu
IPC分类号： H04L5/14 , H04L25/24 , H03K19/0185
CPC分类号： H04L5/1423 , H04L25/24
摘要： The present invention provides a driver/receiver pair connected as a repeater circuit which simultaneously transmits and receives information on multiple connected transmission lines. Transceiver circuits are provided which are mirror images of one another to perform the repeater function of the present invention. Each transceiver in the repeater circuit includes a non-inverting buffer stage which produces a signal swing less than the typical Vdd to ground which is typical for common CMOS inverters. The limited swing provides a variable reference input to a differential receiver element. This receiver looks at the incoming signal, and the signal being transmitted from the repeater to determine if the incoming signal is logical "1" or logical "0". This is done on each side of the repeater since the actual voltage level on the wire at the repeater terminal is a composite of the signal received by the repeater and the signal being transmitted by the repeater. By using the repeater, the data rate is doubled and the transmission distance is increased when compared to simplex unidirectional operation.
摘要翻译：本发明提供了作为中继器电路连接的驱动器/接收器对，其同时发送和接收关于多个连接的传输线的信息。提供收发电路，它们是彼此的镜像，以执行本发明的中继器功能。中继器电路中的每个收发器包括一个非反相缓冲级，其产生比常见的CMOS反相器典型的典型Vdd对地的信号摆幅。限制摆动为差分接收器元件提供可变参考输入。该接收机查看输入信号，并且从中继器发送信号以确定输入信号是逻辑“1”还是逻辑“0”。这是在中继器的每一侧进行的，因为中继器终端上的导线上的实际电压电平是由中继器接收的信号和由中继器传输的信号的组合。通过使用中继器，与单向单向操作相比，数据速率加倍，传输距离增加。

2. 发明授权

US07095788B1 Circuit for facilitating simultaneous multi-directional transmission of multiple signals between multiple circuits using a single transmission line 失效
标题翻译：用于促进使用单个传输线在多个电路之间同时多方向传输多个信号的电路
公开(公告)号：US07095788B1
公开(公告)日：2006-08-22
申请号：US09640802
申请日：2000-08-17
申请人： Tai Anh Cao , Lloyd Andre Walls
发明人： Tai Anh Cao , Lloyd Andre Walls
IPC分类号： H04B3/00 , H04L25/00
CPC分类号： H03K17/693
摘要： An encoding element (109, 111, 113) and a decoding arrangement (110, 112, 114) is included with each separate circuit (104, 105, 106) in a system (100) of circuits which must communicate digital signals with each other. The encoding devices (109, 111, 113) included with the separate circuits (104, 105, 106) cooperate to produce an encoded signal on a common transmission line or network (108) which interconnects the various circuits. The decoding arrangement (110, 112, 114) associated with each respective circuit receives the encoded signal appearing on the transmission line and decodes the encoded signal to reproduce or recreate the digital data signals transmitted from the other circuits in the system.
摘要翻译：编码元件（109,111,113）和解码装置（110,112,114）包括在必须相互通信数字信号的电路系统（100）中的每个分离电路（104,105,106）。包括在分离电路（104,105,106）中的编码装置（109,111,113）协作以在互连各种电路的公共传输线或网络（108）上产生编码信号。与每个相应电路相关联的解码装置（110,112,114）接收出现在传输线上的编码信号，并对编码信号进行解码，以再现或重建从系统中其他电路发送的数字数据信号。

3. 发明授权

US06914849B2 Method and apparatus for reducing power consumption in a memory array with dynamic word line driver/decoders 失效
标题翻译：用于通过动态字线驱动器/解码器降低存储器阵列功耗的方法和装置
公开(公告)号：US06914849B2
公开(公告)日：2005-07-05
申请号：US10687238
申请日：2003-10-16
申请人： Tai Anh Cao , Sam Gat-Shang Chu , Joseph J. McGill IV , Michael Thomas Vaden
发明人： Tai Anh Cao , Sam Gat-Shang Chu , Joseph J. McGill IV , Michael Thomas Vaden
IPC分类号： G11C7/10 , G11C7/22 , G11C8/08 , G11C8/18 , G11C8/00
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/22 , G11C7/225 , G11C8/08 , G11C8/18
摘要： A memory array includes a storage unit with a number of sections and decoders coupled to respective ones of the sections for decoding an N-bit address signal and responsively asserting a signal on one of the word lines selected by the address signal. Local clock buffers are coupled to respective ones of the decoders for receiving a clock signal and an address signal including M most-significant bits of the N-bit address signal and generating respective timing signals. The decoders receive the timing signal from their respective local clock buffers. Each decoder is operable to alternately precharge and evaluate the N-bit address signal responsive to phases of the timing signal. Each local clock buffer is operable, responsive to a state of the M bits of the address signal, for selecting between holding its timing signal in a deasserted state and enabling its timing signal to follow the clock signal.
摘要翻译：存储器阵列包括存储单元，其具有多个部分和解码器，所述部分和解码器耦合到相应的部分，用于对N位地址信号进行解码，并响应地确定由地址信号选择的一条字线上的信号。本地时钟缓冲器耦合到解码器中的相应解码器，用于接收时钟信号和包括N位地址信号的M个最高有效位的地址信号并产生相应的定时信号。解码器从其各自的本地时钟缓冲器接收定时信号。每个解码器可操作以响应于定时信号的相位交替地预充电和评估N位地址信号。每个本地时钟缓冲器可操作地响应于地址信号的M位的状态，用于在保持其定时信号处于无效状态并使其定时信号跟随时钟信号之间进行选择。

4. 发明授权

US06771675B1 Method for facilitating simultaneous multi-directional transmission of multiple signals between multiple circuits using a single transmission line 有权
标题翻译：用于促进使用单个传输线在多个电路之间同时多方向传输多个信号的方法
公开(公告)号：US06771675B1
公开(公告)日：2004-08-03
申请号：US09640770
申请日：2000-08-17
申请人： Tai Anh Cao , Lloyd Andre Walls
发明人： Tai Anh Cao , Lloyd Andre Walls
IPC分类号： H04J302
CPC分类号： H04L5/04
摘要： Digital signals from a group of three or more circuits (104, 105, 106) are used to create an encoded or combined signal on a common transmission line (108). The encoded signal is then decoded at each different circuit to produce or recreate the digital signal asserted by each different circuit in the group. The encoded signal comprises a signal included in a set of unique signal values, with each signal in the set corresponding to a different combination of digital signals asserted by the group of circuits. Decoding the encoded signal at each circuit (104, 105, 106) in the group involves comparing the encoded signal to a particular reference voltage from a set of reference voltages. A particular reference voltage used in this comparison may be selected using one or more digital signals already decoded from the encoded signal.
摘要翻译：来自一组三个或更多个电路（104,105,106）的数字信号用于在公共传输线（108）上创建编码或组合的信号。然后在每个不同的电路处解码编码的信号以产生或重建由组中的每个不同电路断言的数字信号。编码信号包括包含在一组唯一信号值中的信号，集合中的每个信号对应于该组电路断言的数字信号的不同组合。在组中的每个电路（104,105,106）处对编码信号进行解码包括将编码信号与来自一组参考电压的特定参考电压进行比较。可以使用已经从编码信号解码的一个或多个数字信号来选择在该比较中使用的特定参考电压。

5. 发明授权

US06785703B2 Simultaneous dual rail static carry-save-adder circuit using silicon on insulator technology 失效
标题翻译：使用硅绝缘体技术的同时双轨静态进位保存加法器电路
公开(公告)号：US06785703B2
公开(公告)日：2004-08-31
申请号：US09864137
申请日：2001-05-24
申请人： Douglas Hooker Bradley , Tai Anh Cao , Robert Alan Philhower
发明人： Douglas Hooker Bradley , Tai Anh Cao , Robert Alan Philhower
IPC分类号： G06F750
CPC分类号： G06F7/5016
摘要： An adder circuit is provided that generates the sum and sum complement (sum_) signals by constructing the logic in such a way that various levels of both N-type devices and P-type devices are both “on” at the same when that leg is to be open. The logic is then determined by another level and only one P or N type device is on at a given time. For carry and carry complement (carry_) signals a circuit is provided that is symmetrical with respect to P and N devices. The carry and carry_ signals are generated by inputting the complement signals to the same circuit used to generate the carry signal. The symmetrical P and N type devices are complementary in that associated devices are on or off with respect to each other. Both the carry and carry_ signals are concurrently output. The symmetric nature of the static, dual rail, simultaneous, sum and carry circuits will improve switching performance and minimize the floating body effect that can be found in silicon on insulator (SOI) devices.
摘要翻译：提供了一种加法器电路，其通过以这样的方式构造逻辑来产生和和和和（sum_）信号，使得N型装置和P型装置的各种级别在相同时都是“开”的，要开放然后逻辑由另一个级别确定，并且在给定时间只有一个P或N型设备处于打开状态。对于进位和进位补码（carry_）信号，提供相对于P和N器件对称的电路。通过将补码信号输入到用于产生进位信号的相同电路来产生进位和进位信号。对称的P和N型装置是互补的，因为相关联的装置相对于彼此打开或关闭。进位和进位信号同时输出。静态，双轨，同时，和和携带电路的对称性质将提高开关性能并最大限度地减少在绝缘体上硅（SOI）器件中可以发现的浮体效应。

6. 发明授权

US6023183A Voltage conversion circuit and method 失效
标题翻译：电压转换电路及方法
公开(公告)号：US6023183A
公开(公告)日：2000-02-08
申请号：US094906
申请日：1998-06-15
申请人： Tai Anh Cao , Khanh Tuan Vu Nguyen , Hieu Trong Ngo
发明人： Tai Anh Cao , Khanh Tuan Vu Nguyen , Hieu Trong Ngo
IPC分类号： H03L5/00
CPC分类号： H03K19/018521
摘要： A voltage converter circuit (10) includes a primary P-type FET (20) having its source-drain conduction path connected between an input (22) and a first output node (23). An N-type FET (21) is connected in parallel with the primary P-type device (20) between the input (22) and first output node (23). The gate electrode of the primary P-type device (20) is connected to the first output node (23) while the gate electrode of the N-type device (21) is connected to a second voltage supply at the voltage level of a desired second voltage signal. A first digital signal at a first voltage level is applied to the input (22). The voltage produced at the first output node (23) equals the desired second voltage level and comprises the input signal voltage reduced by the threshold voltage of the primary P-type device (20). One or more additional P-type devices (40) may be connected in series with the primary P-type device (20) to reduce the output voltage level further.
摘要翻译：电压转换器电路（10）包括其源极 - 漏极导电路径连接在输入端（22）和第一输出节点（23）之间的初级P型FET（20）。 N型FET（21）与输入（22）和第一输出节点（23）之间的初级P型器件（20）并联连接。初级P型器件（20）的栅电极连接到第一输出节点（23），而N型器件（21）的栅电极以所需的电压电平连接到第二电压源第二电压信号。将第一电压电平的第一数字信号施加到输入端（22）。在第一输出节点（23）处产生的电压等于期望的第二电压电平，并且包括被初级P型装置（20）的阈值电压降低的输入信号电压。一个或多个附加的P型装置（40）可以与初级P型装置（20）串联连接，以进一步降低输出电压电平。

7. 发明授权

US07290027B2 Circuit suitable for use in a carry lookahead adder 有权
标题翻译：电路适用于进位前置加法器
公开(公告)号：US07290027B2
公开(公告)日：2007-10-30
申请号：US10059554
申请日：2002-01-30
申请人： Douglas Hooker Bradley , Tai Anh Cao
发明人： Douglas Hooker Bradley , Tai Anh Cao
IPC分类号： G06F7/50
CPC分类号： G06F7/508
摘要： An adder circuit for determining the sum of two operands including a set of PGK circuits, at least one tier of group circuits, and a carry generation circuit. The PGK circuits generate propagate, generate, and kill bits corresponding to at least a portion of the first and second operands. The group circuit receives propagate, generate, and kill bits from a plurality of the PGK circuits and produces a set of group propagate, generate, and kill values. The carry generation circuit receives a carry-in bit and the outputs of at least one of the group circuits and generates a carry-out bit representing the carry-out of the corresponding group. The PGK circuits, group circuits, and carry circuits may use CMOS transmission gates in lieu of conventional complementary pass-gate logic (CPL).
摘要翻译：一个加法器电路，用于确定包括一组PGK电路，至少一个组电路层和一个进位发生电路的两个操作数之和。 PGK电路产生对应于第一和第二操作数的至少一部分的传播，生成和杀死位。组电路从多个PGK电路接收传播，生成和杀死位，并产生一组群传播，生成和杀死值。进位发生电路接收进位位和组电路中的至少一个的输出，并生成表示相应组的进位输出的进位位。 PGK电路，组电路和进位电路可以使用CMOS传输门来代替传统的互补通道逻辑（CPL）。

8. 发明授权

US06711633B2 4:2 compressor circuit for use in an arithmetic unit 失效
标题翻译： 4：2用于运算单元的压缩机电路
公开(公告)号：US06711633B2
公开(公告)日：2004-03-23
申请号：US10059607
申请日：2002-01-30
申请人： Douglas Hooker Bradley , Tai Anh Cao , Robert Alan Philhower , Wai Yin Wong
发明人： Douglas Hooker Bradley , Tai Anh Cao , Robert Alan Philhower , Wai Yin Wong
IPC分类号： G06F300
CPC分类号： G06F7/607 , G06F7/5318
摘要： A compressor circuit suitable for use in an arithmetic unit of a microprocessor includes a first stage, a second stage, a carry circuit, and a sum circuit. The first stage is configured to receive a set of four input signals. The first stage generates a first intermediate signal indicative of the XNOR of a first pair of the input signals and a second intermediate signal indicative of the XNOR of a second pair of the input signals. The second stage configured to receive at least a portion of the signals generated by the first stage. The second stage generates first and second control signals where the first control signal is indicative of the XNOR of the four input signals and the second control signal is the logical complement of the first signal. The carry circuit is configured to receive at least one of the control signals and further configured to generate a carry bit based at least in part on the state of the received control signal. The sum circuit is configured to receive at least one of the control signals and further configured to generate a sum bit based at least in part on the state of the received control signal. At least one of the first stage, second stage, sum circuit, and carry circuit include at least one CMOS transmission gate comprised of an n-channel transistor and a p-channel transistor having their source/drain terminals connected in parallel, wherein the p-channel transistor gate is driven by the logical complement of the n-channel transistor gate. In one embodiment, the first stage, second stage, carry circuit, and sum circuit are comprised primarily of such transmission gates to the exclusion of conventional CMOS complementary passgate logic.
摘要翻译：适用于微处理器运算单元的压缩机电路包括第一级，第二级，进位电路和和电路。第一级被配置为接收一组四个输入信号。第一级产生指示第一对输入信号的XNOR的第一中间信号和指示第二对输入信号的XNOR的第二中间信号。第二级被配置为接收由第一级产生的信号的至少一部分。第二级产生第一和第二控制信号，其中第一控制信号指示四个输入信号的XNOR，第二控制信号是第一信号的逻辑补码。进位电路被配置为接收至少一个控制信号，并且还被配置为至少部分地基于所接收的控制信号的状态来产生进位位。总和电路被配置为接收至少一个控制信号，并且还被配置为至少部分地基于所接收的控制信号的状态来产生和位。第一级，第二级，和电路和进位电路中的至少一个包括由n沟道晶体管和p沟道晶体管组成的至少一个CMOS传输门，其源极/漏极端子并联连接，其中p 通道晶体管栅极由n沟道晶体管栅极的逻辑补码驱动。在一个实施例中，第一级，第二级，进位电路和和电路主要由这样的传输门组成，以排除常规CMOS互补门极逻辑。

9. 发明授权

US5761246A Circuit for multiplexing a plurality of signals on one transmission line between chips 失效
标题翻译：用于在芯片之间的一个传输线上复用多个信号的电路
公开(公告)号：US5761246A
公开(公告)日：1998-06-02
申请号：US514633
申请日：1995-08-14
申请人： Tai Anh Cao , Satyajit Dutta , Thai Quoc Nguyen , Thanh Doan Trinh , Lloyd Andre Walls
发明人： Tai Anh Cao , Satyajit Dutta , Thai Quoc Nguyen , Thanh Doan Trinh , Lloyd Andre Walls
IPC分类号： H04B3/02 , H04L5/04 , H04L25/49 , H04B3/00
CPC分类号： H04L5/04 , H04B3/02
摘要： The present invention allows for the simultaneous transmission of three digital signals from one integrated circuit to another. The three digital signals are encoded utilizing series resistors of predetermined values and are then transmitted by one transmission line to the second integrated circuit chip. The second integrated circuit chip decodes the first digital signal and then utilizes this decoded first digital signal to further decode the second digital signal, and then utilizes the decoded first and second digital signals to decode the third digital signal.
摘要翻译：本发明允许从一个集成电路到另一个集成电路的三个数字信号的同时传输。三个数字信号利用预定值的串联电阻进行编码，然后由一个传输线传输到第二集成电路芯片。第二集成电路芯片对第一数字信号进行解码，然后利用该解码的第一数字信号进一步解码第二数字信号，然后利用解码的第一和第二数字信号对第三数字信号进行解码。

10. 发明授权

US06970798B1 Method, apparatus and computer program product for high speed memory testing 失效
标题翻译：用于高速内存测试的方法，设备和计算机程序产品
公开(公告)号：US06970798B1
公开(公告)日：2005-11-29
申请号：US10840559
申请日：2004-05-06
申请人： Tai Anh Cao , Khanh Nguyen , Aquilur Rahman
发明人： Tai Anh Cao , Khanh Nguyen , Aquilur Rahman
IPC分类号： G06F19/00
CPC分类号： G06F11/263 , G06F11/273
摘要： For testing a device under test (“DUT”) a test specification is converted in a computer system by a pin vector generator process, which includes generating test vectors. The DUT has numerous input pins and such a pin vector is for a signal to drive one such pin. The pin vectors are compressed and saved. Ones of the pin vectors are loaded, upon initialization of a test, into a pipeline having a series of memory stages and extending from the computer system to channel cards in a test head. The pipeline is operated in data transfer cycles, delivering W bits per cycle. The pin vectors are decompressed at the respective channel cards in decompressor read cycles. X bits are read per decompressor cycle, W being greater than X, so that the pipeline may perform its data transfer cycles less frequently than the decompressor performs its read cycles.
摘要翻译：为了测试被测设备（“DUT”），测试规范在计算机系统中通过引脚向量生成器进程进行转换，其中包括生成测试向量。 DUT具有许多输入引脚，并且这样的引脚矢量用于信号来驱动一个这样的引脚。引脚向量被压缩并保存。在测试初始化时，引导向量的载入被加载到具有一系列存储器级并且从计算机系统延伸到测试头中的通道卡的管道中。流水线在数据传输周期中运行，每个周期提供W位。在解压缩器读取周期中，引脚向量在相应的通道卡处被解压缩。每个解压缩器周期读取X位，W大于X，使得流水线可以比解压缩器执行其读周期更不频繁地执行其数据传送周期。

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