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1. 发明授权

US5543649A Electrostatic discharge protection device for a semiconductor circuit 失效
标题翻译：一种用于半导体电路的静电放电保护装置
公开(公告)号：US5543649A
公开(公告)日：1996-08-06
申请号：US396142
申请日：1995-03-01
申请人： Tae-Han Kim , Sang-Hoon Lee , Dae-Je Chin
发明人： Tae-Han Kim , Sang-Hoon Lee , Dae-Je Chin
IPC分类号： H01L29/78 , H01L27/02 , H01L27/04 , H01L23/62
CPC分类号： H01L27/0266 , H01L27/0259
摘要： The present invention provides an electrostatic discharge protection device of a semiconductor memory device which comprises a gate and a bulk region of first conduction type which are commonly connected to a first power supply, a first diffused region of second conduction type formed in the bulk region, isolated from the gate by a dielectric and connected to the second power supply, and a second diffused region of second conduction type separated from the first diffused region in the bulk region, isolated from the gate by the dielectric and connected to the signal voltage.
摘要翻译：本发明提供一种半导体存储器件的静电放电保护器件，其包括通常连接到第一电源的栅极和主区域，第一导电类型的主体区域，形成在本体区域中的第二导电类型的第一扩散区域，通过电介质隔离并连接到第二电源，以及与主体区域中的第一扩散区分离的第二扩散区域，其通过电介质与栅极隔离并连接到信号电压。

2. 发明授权

US5432365A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5432365A
公开(公告)日：1995-07-11
申请号：US38842
申请日：1993-03-09
申请人： Dae-Je Chin , Chang-Hyun Kim
发明人： Dae-Je Chin , Chang-Hyun Kim
IPC分类号： H01L27/04 , H01L21/334 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/94 , H01L29/68 , H01L27/02
CPC分类号： H01L27/10861 , H01L27/10829 , H01L29/66181 , H01L29/945
摘要： There is disclosed a memory cell made with a semiconductor substrate for mounting integrated circuit elements, and having a trench for forming a capacitor region extending vertically to the surface of the substrate. In the substrate region around the trench is formed a cell plate region of second conductivity type for forming a charge storage region within the capacitor region. A high concentration semiconductor region of the same conductivity type as the substrate is formed in the substrate region outside the cell plate region to increase the charge stored in the capacitor region. A conducting material stores charge responding to the voltage given within the trench. A dielectric layer is formed between the conducting material and the cell plate.
摘要翻译：公开了一种由半导体衬底制成的用于安装集成电路元件的存储单元，并且具有用于形成垂直于衬底表面延伸的电容器区域的沟槽。在沟槽周围的衬底区域中形成第二导电类型的单元板区域，用于在电容器区域内形成电荷存储区域。在电池板区域外部的基板区域中形成与基板相同的导电类型的高浓度半导体区域，以增加存储在电容器区域中的电荷。导电材料存储响应于在沟槽内给出的电压的电荷。在导电材料和电池板之间形成介电层。

3. 发明授权

US5378908A Stack capacitor DRAM cell having increased capacitor area 失效
标题翻译：堆叠电容器DRAM单元具有增加的电容器面积
公开(公告)号：US5378908A
公开(公告)日：1995-01-03
申请号：US283968
申请日：1988-12-13
申请人： Dae-Je Chin , Tae-Young Chung
发明人： Dae-Je Chin , Tae-Young Chung
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78 , H01L29/92
CPC分类号： H01L27/10852 , H01L27/10808
摘要： A saddled and wrapped stack capacitor DRAM and a method thereof are provided. The DRAM of the invention includes three factors in increasing the effective area for a capacitor. One is a storage poly layer comprising a first poly layer and a second poly layer, which is formed thick in a region over a field oxide layer through two steps; another is a spacer which is formed through an etchback technique for an oxide layer coated on another oxide layer being patterened to selectively remove the storage poly layer, and the spacer maximizes the size of the storage poly; another is an undercut which is formed in boundary regions on an upper oxide layer, on which a plat poly material is coated and wrapped.
摘要翻译：提供了一种叠置和堆叠的堆叠电容器DRAM及其方法。本发明的DRAM包括增加电容器有效面积的三个因素。一种是存储多层，其包括第一多晶层和第二多晶硅层，其通过两个步骤在场氧化物层上的区域中形成为厚; 另一个是通过蚀刻技术形成的间隔物，其中涂覆在另一氧化物层上的氧化物层被选择性地选择性地去除存储多晶硅层，并且间隔物使存储聚硅的尺寸最大化; 另一种是在上氧化物层上的边界区域上形成底切，在其上涂覆和包裹平板状多层材料。

4. 发明授权

US5610869A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5610869A
公开(公告)日：1997-03-11
申请号：US511815
申请日：1995-08-07
申请人： Seung-Moon Yoo , Ejaz ul Haq , Yun-Ho Choi , Soo-In Cho , Dae-Je Chin , Nam-Soo Kang , Seung-Hun Lee
发明人： Seung-Moon Yoo , Ejaz ul Haq , Yun-Ho Choi , Soo-In Cho , Dae-Je Chin , Nam-Soo Kang , Seung-Hun Lee
IPC分类号： G11C5/14 , H02M3/07 , G11C13/00
CPC分类号： H02M3/07 , G11C5/145
摘要： A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.
摘要翻译：半导体存储器件通过包括用于根据电源电压的预定电平产生检测信号的电源电压电平检测器和用于产生频率为...的频率控制的振荡脉冲的振荡器，稳定地在宽范围的电源电压下工作根据检测信号可变。因此，升压电路的升压比，刷新电路的刷新周期和基板电压发生器的基板电压可以根据电源电压的变化自适应地变化。

5. 发明授权

US5359560A Semiconductor memory device having improved redundancy efficiency 失效
标题翻译：具有提高的冗余效率的半导体存储器件
公开(公告)号：US5359560A
公开(公告)日：1994-10-25
申请号：US162467
申请日：1993-12-07
申请人： Dong-Il Suh , Tae-Sung Jang , Dae-Je Chin
发明人： Dong-Il Suh , Tae-Sung Jang , Dae-Je Chin
IPC分类号： G11C29/00 , G11C29/04 , G11C13/00
CPC分类号： G11C29/808
摘要： A row redundancy circuit for use in a semiconductor memory device. The row redundancy circuit providing fuse boxes to repair defective normal memory cells even in the adjacent normal memory cell arrays.
摘要翻译：一种用于半导体存储器件的行冗余电路。行冗余电路提供熔丝盒以修复有缺陷的正常存储单元，甚至在相邻的正常存储单元阵列中。

6. 发明授权

US5130580A Sense amplifier driving circuit employing current mirror for semiconductor memory device 失效
标题翻译：使用半导体存储器件的电流镜的感应放大器驱动电路
公开(公告)号：US5130580A
公开(公告)日：1992-07-14
申请号：US550997
申请日：1990-07-11
申请人： Dong-sun Min , Hong-sun Hwang , Soo-in Cho , Dae-Je Chin
发明人： Dong-sun Min , Hong-sun Hwang , Soo-in Cho , Dae-Je Chin
IPC分类号： G11C11/419 , G11C7/06 , G11C11/407 , G11C11/409
CPC分类号： G11C7/065
摘要： A sense amplifier driving circuit for controlling sense amplifiers of high density semiconductor memory device by turning-on/off a driving transistor connected between an external voltage Vcc terminal and a ground voltage Vss terminal, comprises a bias circuit including a MOS transistor being connected to the driving MOS transistor to form a current mirror circuit therewith which is controlled by a sense amplifier enable clock and a constant current source having a MOS transistor with a bias voltage of an intermediate level between Vcc and Vss being applied to its gate terminal. The bias circuit is connected to the gate terminal of the driving transistor to control the gate voltage of the driving transistor, thereby reducing the peak current of a sense amplifier driving signal. Further, the driving signals are generated in the waveform having a linear dual slope, resulting in a decrease in power-noise. The bias circuit is connected to a clamping circuit having a comparator circuit to clamp the active restore voltage of the sense amplifier driving circuit, so that the active restore voltage can be maintained at the level of an internal voltage (approximately 4V), thereby preventing the distortion of the characteristics of the cell device and eliminating the necessity of additional standby current by enabling the sense amplifier only for the active restore operation. Further, the sense amplifier driving circuit comprises a constant circuit including two or more current mirror circuits which are sequentially activated, whereby the sense amplifier driving signals are made to have stable linear dual slopes.
摘要翻译：一种读出放大器驱动电路，用于通过接通/断开连接在外部电压Vcc端子和接地电压Vss端子之间的驱动晶体管来控制高密度半导体存储器件的读出放大器，包括：偏置电路，包括MOS晶体管，连接到驱动MOS晶体管与其形成电流镜像电路，其由读出放大器使能时钟控制，并且具有MOS晶体管的恒定电流源，其中Vcc和Vss之间的中间电平的偏置电压被施加到其栅极端子。偏置电路连接到驱动晶体管的栅极端子，以控制驱动晶体管的栅极电压，从而降低读出放大器驱动信号的峰值电流。此外，在具有线性双斜率的波形中产生驱动信号，导致功率噪声的降低。偏置电路连接到具有比较器电路的钳位电路，以钳位读出放大器驱动电路的有效恢复电压，使得有效恢复电压可以保持在内部电压（大约4V）的水平，从而防止通过使感测放大器仅用于主动恢复操作，从而消除了电池装置特性的失真，并消除了额外待机电流的必要性。此外，读出放大器驱动电路包括一个恒定电路，该恒定电路包括被依次激活的两个或多个电流镜电路，从而使读出放大器驱动信号具有稳定的线性双斜率。

7. 发明授权

US5760791A Graphic RAM having a dual port and a serial data access method thereof 失效
标题翻译：具有双端口的图形RAM及其串行数据访问方法
公开(公告)号：US5760791A
公开(公告)日：1998-06-02
申请号：US378277
申请日：1995-01-26
申请人： Seong-Ook Jung , Seung-Mo Seo , Dae-Je Chin
发明人： Seong-Ook Jung , Seung-Mo Seo , Dae-Je Chin
IPC分类号： G11C11/401 , G09G5/395 , G11C7/10 , G09G5/36
CPC分类号： G09G5/395 , G11C7/1075
摘要： A graphic RAM array has a plurality of sub blocks which share random and serial output paths. This structure enables random access to the random output path of one RAM array while a specific sub block of another other RAM array is performing a display operation via the serial output path. The graphic RAM does not have a separate data register and outputs the serial data using only the RAM array. Thus, only the RAM array is formed in the cell core region, thereby reducing the size and price of the chip. In addition, it is possible for the graphic RAM to be compatible with a system having a conventional video RAM controller.
摘要翻译：图形RAM阵列具有共享随机和串行输出路径的多个子块。该结构能够随机访问一个RAM阵列的随机输出路径，而另一个RAM阵列的特定子块通过串行输出路径执行显示操作。图形RAM不具有单独的数据寄存器，仅使用RAM阵列输出串行数据。因此，在单元芯区域中仅形成RAM阵列，从而减小芯片的尺寸和价格。此外，图形RAM可以与具有常规视频RAM控制器的系统兼容。

8. 发明授权

US5446697A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5446697A
公开(公告)日：1995-08-29
申请号：US068547
申请日：1993-05-28
申请人： Seung-Moon Yoo , Ejaz ul Haq , Yun-Ho Choi , Soo-In Cho , Dae-Je Chin , Nam-Soo Kang , Seung-Hun Lee
发明人： Seung-Moon Yoo , Ejaz ul Haq , Yun-Ho Choi , Soo-In Cho , Dae-Je Chin , Nam-Soo Kang , Seung-Hun Lee
IPC分类号： G11C5/14 , H02M3/07 , G11C13/00
CPC分类号： H02M3/07 , G11C5/145
摘要： A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.
摘要翻译：半导体存储器件通过包括用于根据电源电压的预定电平产生检测信号的电源电压电平检测器和用于产生频率为...的频率控制的振荡脉冲的振荡器，稳定地在宽范围的电源电压下工作根据检测信号可变。因此，升压电路的升压比，刷新电路的刷新周期和基板电压发生器的基板电压可以根据电源电压的变化自适应地变化。

9. 发明授权

US5343438A Semiconductor memory device having a plurality of row address strobe signals 失效
标题翻译：具有多个行地址选通信号的半导体存储器件
公开(公告)号：US5343438A
公开(公告)日：1994-08-30
申请号：US9475
申请日：1993-02-01
申请人： Yun-Ho Choi , Dae-Je Chin , Ejaz U. Haq , Soo-In Cho
发明人： Yun-Ho Choi , Dae-Je Chin , Ejaz U. Haq , Soo-In Cho
IPC分类号： G11C11/401 , G06F12/02 , G11C8/18 , G11C11/407 , G11C11/4076 , G11C11/409 , G11C8/00
CPC分类号： G11C8/18 , G11C11/4076
摘要： The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory for accomplishing high speed data access by supplying a plurality of row address strobe signals to a chip. A plurality of row address strobe signals are supplied to a plurality of pins, and each row address strobe signal is sequentially supplied with an active signal during a data access operation. Therefore, data in a plurality of memory cell arrays is accessed during one access cycle time. Thus, since a large number of random data are provided, the data access time decreases and the performance of a system can be greatly improved.
摘要翻译：本发明涉及一种半导体存储器件，更具体地说，涉及通过向芯片提供多个行地址选通信号来实现高速数据存取的动态随机存取存储器。多个行地址选通信号被提供给多个引脚，并且每个行地址选通信号在数据访问操作期间被依次提供有效信号。因此，在一个访问周期时间内访问多个存储单元阵列中的数据。因此，由于提供大量随机数据，所以数据访问时间减少，并且可以大大提高系统的性能。

10. 再颁专利

USRE36261E Stack capacitor DRAM cell having increased capacitor area 失效
标题翻译：堆叠电容器DRAM单元具有增加的电容器面积
公开(公告)号：USRE36261E
公开(公告)日：1999-08-03
申请号：US761082
申请日：1996-12-04
申请人： Dae-Je Chin , Tae-Young Chung
发明人： Dae-Je Chin , Tae-Young Chung
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78 , H01L29/92
CPC分类号： H01L27/10852 , H01L27/10808
摘要： A saddled and wrapped stack capacitor DRAM and a method thereof are provided. The DRAM of the invention includes three factors in increasing the effective area for a capacitor. One is a storage poly layer comprising a first poly layer and a second poly layer, which is formed thick in a region over a field oxide layer through two steps; another is a spacer which is formed through an etchback technique for an oxide layer coated on another oxide layer being patterened to selectively remove the storage poly layer, and the spacer maximizes the size of the storage poly; another is an undercut which is formed in boundary regions on an upper oxide layer, on which a .�.plat.!. .Iadd.plate .Iaddend.poly material is coated and wrapped.
摘要翻译：提供了一种叠置和堆叠的堆叠电容器DRAM及其方法。本发明的DRAM包括增加电容器有效面积的三个因素。一种是存储多层，其包括第一多晶层和第二多晶硅层，其通过两个步骤在场氧化物层上的区域中形成为厚; 另一个是通过蚀刻技术形成的间隔物，其中涂覆在另一氧化物层上的氧化物层被选择性地选择性地去除存储多晶硅层，并且间隔物使存储聚硅的尺寸最大化; 另一种是在上部氧化物层上的边界区域上形成底切，在其上涂覆并包裹有[平板]多晶材料。

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