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1. 发明申请

US20080303120A1 Semiconductor chip package 有权
标题翻译：半导体芯片封装
公开(公告)号：US20080303120A1
公开(公告)日：2008-12-11
申请号：US12155867
申请日：2008-06-11
申请人： Tae Soo Lee , Yun Hwi Park
发明人： Tae Soo Lee , Yun Hwi Park
IPC分类号： H01L23/552
CPC分类号： H01L23/552 , H01L23/13 , H01L23/15 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L2224/16225 , H01L2224/16235 , H01L2224/32225 , H01L2224/451 , H01L2224/48227 , H01L2224/48235 , H01L2224/73253 , H01L2224/73265 , H01L2224/81801 , H01L2224/85 , H01L2924/09701 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H01L2924/15787 , H01L2924/16152 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： A semiconductor chip package includes a main board; a ceramic substrate having a cavity within which at least one chip is electrically mounted, the cavity being placed at a lower portion of the ceramic substrate facing the main board; and a conductive shielding layer provided with a predetermined thickness on the outside of the ceramic substrate. The ceramic substrate includes: at least one first ground line electrically connecting the conductive shielding layer with the main board; at least one second ground line electrically connecting the conductive shielding layer with the chip; and at least one signal line electrically connecting the chip with the main board. Thus, manufacturing costs are lowered because of the reduced number of components being used, miniaturization in device design can be achieved because of the small volume of the package, and the ground performance can be improved.
摘要翻译：半导体芯片封装包括主板; 陶瓷基板，其具有至少一个芯片电气安装的空腔，所述空腔设置在所述陶瓷基板的面对所述主板的下部; 以及在陶瓷基板的外侧设置有规定厚度的导电性屏蔽层。陶瓷基板包括：将导电屏蔽层与主板电连接的至少一个第一接地线; 将所述导电屏蔽层与所述芯片电连接的至少一个第二接地线; 以及将芯片与主板电连接的至少一个信号线。因此，由于使用的部件数量减少，制造成本降低，因为可以实现小型化的装置设计，因为包装体积小，并且可以提高地面性能。

2. 发明申请

US20100102430A1 SEMICONDUCTOR MULTI-CHIP PACKAGE 审中-公开
标题翻译：半导体多芯片封装
公开(公告)号：US20100102430A1
公开(公告)日：2010-04-29
申请号：US12476221
申请日：2009-06-01
申请人： Tae Soo LEE , Yun Hwi Park , Yun Hee Cho
发明人： Tae Soo LEE , Yun Hwi Park , Yun Hee Cho
IPC分类号： H01L23/488 , H01L23/48
CPC分类号： H01L25/16 , H01L24/73 , H01L2224/05554 , H01L2224/16227 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06541 , H01L2225/06572 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/07802 , H01L2924/09701 , H01L2924/14 , H01L2924/15787 , H01L2924/181 , H01L2924/19104 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor multichip package includes a substrate having a top surface on which a bonding pad is formed, and a bottom surface opposing the top surface, on which an external connection terminal electrically connected with the bonding pad is formed, a first semiconductor chip mounted on a region of the top surface of the substrate excluding the bonding pad, a ceramic spacer disposed on a top surface of the first semiconductor chip and including a passive device therein, and at least one second semiconductor chip disposed on a top surface of the ceramic spacer. The ceramic spacer includes an interlayer circuit for an electrical connection between the first and second semiconductor chips, and the passive device is electrically connected to at least one of the first and second semiconductor chips. Accordingly, a package with a more compact structure can be realized.
摘要翻译：一种半导体多芯片封装，包括具有形成有焊盘的顶面的基板和与形成有与焊盘电连接的外部连接端子的上表面的底面，安装在焊盘上的第一半导体芯片除了焊盘之外的衬底的顶表面的区域，设置在第一半导体芯片的顶表面上并且包括其中的无源器件的陶瓷间隔件和设置在陶瓷间隔件的顶表面上的至少一个第二半导体芯片。陶瓷间隔件包括用于第一和第二半导体芯片之间的电连接的层间电路，并且无源器件电连接到第一和第二半导体芯片中的至少一个。因此，可以实现具有更紧凑结构的封装。

3. 发明申请

US20100105171A1 SEMICONDUCTOR CHIP, METHOD OF MANUFACTURING THE SEMICONDUCTOR CHIP AND SEMICONDUCTOR CHIP PACKAGE 失效
标题翻译：半导体芯片，制造半导体芯片和半导体芯片封装的方法
公开(公告)号：US20100105171A1
公开(公告)日：2010-04-29
申请号：US12651234
申请日：2009-12-31
申请人： Tae Soo LEE , Yun Hwi Park
发明人： Tae Soo LEE , Yun Hwi Park
IPC分类号： H01L21/768 , H01L21/78
CPC分类号： H01L23/552 , H01L23/481 , H01L2224/0401 , H01L2224/05568 , H01L2224/0557 , H01L2224/05573 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2224/16227 , H01L2224/274 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/09701 , H01L2924/3025 , H01L2924/00014
摘要： In a semiconductor chip, a body has a top surface where a pattern is formed, an underside surface opposing the top surface and a plurality of side surfaces. A plurality of electrode pads are formed on the top surface of the body to connect to an external terminal. A shielding conductive film is formed on the surfaces excluding the top surface of the body where the pattern is formed. A conductive via is extended through the body to connect one of the electrode pads with the conductive film.
摘要翻译：在半导体芯片中，主体具有形成图案的顶表面，与顶表面相对的下表面和多个侧表面。多个电极焊盘形成在主体的顶表面上以连接到外部端子。在除了形成图案的主体的顶表面之外的表面上形成屏蔽导电膜。导电通孔延伸通过本体以将电极焊盘中的一个与导电膜连接。

4. 发明授权

US08043896B2 Semiconductor chip, method of manufacturing the semiconductor chip and semiconductor chip package including an inclined via hole 失效
标题翻译：半导体芯片，制造半导体芯片的方法和包括倾斜通孔的半导体芯片封装
公开(公告)号：US08043896B2
公开(公告)日：2011-10-25
申请号：US12651234
申请日：2009-12-31
申请人： Tae Soo Lee , Yun Hwi Park
发明人： Tae Soo Lee , Yun Hwi Park
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L23/552 , H01L23/481 , H01L2224/0401 , H01L2224/05568 , H01L2224/0557 , H01L2224/05573 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2224/16227 , H01L2224/274 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/09701 , H01L2924/3025 , H01L2924/00014
摘要： In a semiconductor chip, a body has a top surface where a pattern is formed, an underside surface opposing the top surface and a plurality of side surfaces. A plurality of electrode pads are formed on the top surface of the body to connect to an external terminal. A shielding conductive film is formed on the surfaces excluding the top surface of the body where the pattern is formed. A conductive via is extended through the body to connect one of the electrode pads with the conductive film.
摘要翻译：在半导体芯片中，主体具有形成图案的顶表面，与顶表面相对的下表面和多个侧表面。多个电极焊盘形成在主体的顶表面上以连接到外部端子。在除了形成图案的主体的顶表面之外的表面上形成屏蔽导电膜。导电通孔延伸通过本体以将电极焊盘中的一个与导电膜连接。

5. 发明授权

US07872869B2 Electronic chip module 有权
标题翻译：电子芯片模块
公开(公告)号：US07872869B2
公开(公告)日：2011-01-18
申请号：US12425111
申请日：2009-04-16
申请人： Tae Soo Lee , Yun Hwi Park
发明人： Tae Soo Lee , Yun Hwi Park
IPC分类号： H05K7/20
CPC分类号： H01L23/3677 , H01L23/3737 , H01L2924/0002 , H01L2924/09701 , H05K1/0206 , H05K1/0306 , H05K3/0061 , H05K3/386 , H05K2201/10287 , H01L2924/00
摘要： Provided is an electron chip module having a heat sink that can increase heat dissipation efficiency. A bottom surface of a module circuit board and an upper surface of a heat sink are in direct contact with each other by using a metal wire, such that heat generated during the operation of a heat-generating device chip mounted onto the module circuit board can be effectively dissipated to the outside.
摘要翻译：提供一种具有能够提高散热效率的散热器的电子芯片模块。模块电路板的底面和散热器的上表面通过使用金属线彼此直接接触，使得在安装到模块电路板上的发热装置芯片的操作期间产生的热可以有效地消散到外面。

6. 发明授权

US07745911B2 Semiconductor chip package 有权
标题翻译：半导体芯片封装
公开(公告)号：US07745911B2
公开(公告)日：2010-06-29
申请号：US12155867
申请日：2008-06-11
申请人： Tae Soo Lee , Yun Hwi Park
发明人： Tae Soo Lee , Yun Hwi Park
IPC分类号： H01L23/552
CPC分类号： H01L23/552 , H01L23/13 , H01L23/15 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L2224/16225 , H01L2224/16235 , H01L2224/32225 , H01L2224/451 , H01L2224/48227 , H01L2224/48235 , H01L2224/73253 , H01L2224/73265 , H01L2224/81801 , H01L2224/85 , H01L2924/09701 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H01L2924/15787 , H01L2924/16152 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： A semiconductor chip package includes a main board; a ceramic substrate having a cavity within which at least one chip is electrically mounted, the cavity being placed at a lower portion of the ceramic substrate facing the main board; and a conductive shielding layer provided with a predetermined thickness on the outside of the ceramic substrate. The ceramic substrate includes: at least one first ground line electrically connecting the conductive shielding layer with the main board; at least one second ground line electrically connecting the conductive shielding layer with the chip; and at least one signal line electrically connecting the chip with the main board. Thus, manufacturing costs are lowered because of the reduced number of components being used, miniaturization in device design can be achieved because of the small volume of the package, and the ground performance can be improved.
摘要翻译：半导体芯片封装包括主板; 陶瓷基板，其具有至少一个芯片电气安装的空腔，所述空腔设置在所述陶瓷基板的面对所述主板的下部; 以及在陶瓷基板的外侧设置有规定厚度的导电性屏蔽层。陶瓷基板包括：将导电屏蔽层与主板电连接的至少一个第一接地线; 将所述导电屏蔽层与所述芯片电连接的至少一个第二接地线; 以及将芯片与主板电连接的至少一个信号线。因此，由于使用的部件数量减少，制造成本降低，因为可以实现小型化的装置设计，因为包装体积小，并且可以提高地面性能。

7. 发明申请

US20070267725A1 Semiconductor chip, method of manufacturing the semiconductor chip and semiconductor chip package 审中-公开
标题翻译：半导体芯片，制造半导体芯片的方法和半导体芯片封装
公开(公告)号：US20070267725A1
公开(公告)日：2007-11-22
申请号：US11702131
申请日：2007-02-05
申请人： Tae Soo Lee , Yun Hwi Park
发明人： Tae Soo Lee , Yun Hwi Park
IPC分类号： H01L23/48 , H01L21/4763 , H01L23/552
CPC分类号： H01L23/552 , H01L23/481 , H01L2224/0401 , H01L2224/05568 , H01L2224/0557 , H01L2224/05573 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2224/16227 , H01L2224/274 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/09701 , H01L2924/3025 , H01L2924/00014
摘要： In a semiconductor chip, a body has a top surface where a pattern is formed, an underside surface opposing the top surface and a plurality of side surfaces. A plurality of electrode pads are formed on the top surface of the body to connect to an external terminal. A shielding conductive film is formed on the surfaces excluding the top surface of the body where the pattern is formed. A conductive via is extended through the body to connect one of the electrode pads with the conductive film.
摘要翻译：在半导体芯片中，主体具有形成图案的顶表面，与顶表面相对的下表面和多个侧表面。多个电极焊盘形成在主体的顶表面上以连接到外部端子。在除了形成图案的主体的顶表面之外的表面上形成屏蔽导电膜。导电通孔延伸通过本体以将电极焊盘中的一个与导电膜连接。

8. 发明申请

US20070176302A1 Low temperature co-fired ceramic module and method of manufacturing the same 审中-公开
标题翻译：低温共烧陶瓷模块及其制造方法
公开(公告)号：US20070176302A1
公开(公告)日：2007-08-02
申请号：US11643693
申请日：2006-12-22
申请人： Tae Soo Lee , Yun Hwi Park , Taek Jung Lee
发明人： Tae Soo Lee , Yun Hwi Park , Taek Jung Lee
IPC分类号： H01L23/48 , H01L21/00
CPC分类号： H01L23/49811 , H01L23/15 , H01L24/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/09701 , H01L2924/14 , H01L2924/15787 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , H05K1/0306 , H05K3/246 , H05K3/341 , H05K3/4611 , H05K3/4629 , H05K2201/0347 , H05K2201/10727 , H05K2201/10969 , Y02P70/613 , H01L2924/00
摘要： An LTCC module includes an LTCC substrate and a pad part formed on an undersurface of the LTCC substrate for mounting the LTCC substrate to an external substrate. The pad part includes a metal pad layer formed on an undersurface of the LTCC substrate and a solder layer formed on an undersurface of the metal pad layer.
摘要翻译： LTCC模块包括LTCC基板和形成在LTCC基板的下表面上的焊盘部分，用于将LTCC基板安装到外部基板。焊盘部分包括形成在LTCC衬底的下表面上的金属焊盘层和形成在金属焊盘层的下表面上的焊料层。

9. 发明申请

US20130032384A1 THIN FILM ELECTRODE CERAMIC SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：薄膜电极陶瓷基板及其制造方法
公开(公告)号：US20130032384A1
公开(公告)日：2013-02-07
申请号：US13565249
申请日：2012-08-02
申请人： Won Hee Yoo , Byeung Gyu Chang , Taek Jung Lee , Yun Hwi Park
发明人： Won Hee Yoo , Byeung Gyu Chang , Taek Jung Lee , Yun Hwi Park
IPC分类号： H05K1/03 , H05K3/22
CPC分类号： H05K3/243 , H05K1/0306 , H05K3/107 , H05K3/108 , H05K2201/0338
摘要： Disclosed herein are a thin film electrode ceramic substrate and a method for manufacturing the same. The thin film electrode ceramic substrate includes: a ceramic substrate; a thin film electrode pattern formed on the ceramic substrate; and a plating layer formed on the thin film electrode pattern, wherein the plating layer is formed above the thin film electrode pattern and on both lateral surfaces of the thin film electrode pattern. According to the present invention, an undercut defect occurring between the surface of the ceramic substrate and the thin film electrode pattern and between the thin film electrode patterns due to an etchant can be prevented, by forming a plating layer above the thin film electrode pattern or on both lateral surfaces of the thin film electrode pattern, or forming an intaglio type anti-etching metal layer in the surface of the ceramic substrate.
摘要翻译：本文公开了一种薄膜电极陶瓷基板及其制造方法。薄膜电极陶瓷基板包括：陶瓷基板; 形成在陶瓷基板上的薄膜电极图案; 以及形成在所述薄膜电极图案上的镀层，其中所述镀层形成在所述薄膜电极图案的上方以及所述薄膜电极图案的两个侧面上。根据本发明，通过在薄膜电极图案上方形成镀层，可以防止在陶瓷基板的表面与薄膜电极图案之间以及由于蚀刻剂引起的薄膜电极图案之间发生的底切缺陷，或在薄膜电极图案的两个侧表面上，或在陶瓷基板的表面中形成凹版型的抗蚀刻金属层。

10. 发明申请

US20080238553A1 POWER AMPLIFYING DEVICE HAVING LINEARIZER 失效
标题翻译：具有线性化的功率放大器件
公开(公告)号：US20080238553A1
公开(公告)日：2008-10-02
申请号：US12049005
申请日：2008-03-14
申请人： Yun Hee CHO , Chul Soon Park , Ji Hoon Kim , Yun Hwi Park
发明人： Yun Hee CHO , Chul Soon Park , Ji Hoon Kim , Yun Hwi Park
IPC分类号： H03F3/04
CPC分类号： H03F1/0266 , H03F1/32 , H03F2200/18
摘要： There is provided a power amplifying device having a linearizer in which a bias circuit has an initial impedance set when initially operated, then the impedance is varied according to a level of an input signal and the input signal is amplified in a broad range from a low level region to a high level region, thereby improving linearity of an output signal. The power amplifying device including: an amplifying unit receiving a bias power source and amplifying an input signal; a bias unit varying the bias power source according to a set impedance to provide to the amplifying unit; and an impedance setting unit setting the impedance of the bias unit in response to a preset control voltage when the bias unit is initially operated and re-setting the impedance of the bias unit according to a level of the input signal of the amplifying unit after initial operation of the bias unit.
摘要翻译：提供一种功率放大装置，其具有线性化装置，其中偏置电路在初始操作时具有设定的初始阻抗，然后根据输入信号的电平来改变阻抗，并且输入信号在低范围内被放大电平区域到高电平区域，从而提高输出信号的线性度。功率放大装置包括：放大单元，接收偏置电源并放大输入信号; 偏置单元根据设定的阻抗改变偏置电源以提供给放大单元; 以及阻抗设定单元，当偏置单元初始操作时，响应于预设的控制电压来设定偏置单元的阻抗，并根据放大单元的输入信号的电平在初始化之后重新设置偏置单元的阻抗偏置单元的操作。

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