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1. 发明授权

US6091613A Semiconductor memory device having a multi-step pulse generation circuit 有权
标题翻译：具有多级脉冲发生电路的半导体存储器件
公开(公告)号：US6091613A
公开(公告)日：2000-07-18
申请号：US294349
申请日：1999-04-20
申请人： Tae Hum Yang , Chae Hyun Jung
发明人： Tae Hum Yang , Chae Hyun Jung
IPC分类号： H01L27/04 , H01L27/10 , H02M3/18
CPC分类号： G11C5/147 , G11C16/30
摘要： A voltage generation circuit of a semiconductor memory device has a charge pump circuit for supplying a voltage required to operate the semiconductor memory device; a voltage divide circuit having a plurality of capacitors and connected to the output of the charge pump circuit to divide the output of the charge pump circuit; an initialization means for discharging charges charged to the plurality of capacitors according to a reset signal; and a differential amplifier for controlling the charge pump circuit according to the result of comparison of the voltage divide circuit and a reference voltage.
摘要翻译：半导体存储器件的电压产生电路具有用于提供操作半导体存储器件所需的电压的电荷泵电路; 一个分压电路，具有多个电容器并连接到电荷泵电路的输出端以分频电荷泵电路的输出; 初始化装置，用于根据复位信号对充电到多个电容器的电荷进行放电; 以及差分放大器，用于根据分压电路的比较结果和参考电压来控制电荷泵电路。

2. 发明授权

US6052305A Erasing circuit for a flash memory device having a triple well structure 有权
标题翻译：具有三重阱结构的闪存器件的擦除电路
公开(公告)号：US6052305A
公开(公告)日：2000-04-18
申请号：US143409
申请日：1998-08-28
申请人： Tae Hum Yang , Joo Young Kim , Young Dong Joo , Jong Bae Jeong , Jong Seuk Lee , Il Hyun Choi , Mun Pyo Hong , Chae Hyun Jung
发明人： Tae Hum Yang , Joo Young Kim , Young Dong Joo , Jong Bae Jeong , Jong Seuk Lee , Il Hyun Choi , Mun Pyo Hong , Chae Hyun Jung
IPC分类号： G11C16/04 , G11C16/16
CPC分类号： G11C16/16
摘要： The present invention discloses a flash memory device, a first well and second well are formed in a substrate, a plurality of memory cell are formed in the second well and arranged in an array having a multiplicity of bit lines and word lines. Voltage is applied to the first well and second well, respectively, with time interval so that an over erasing of the memory cell and lowering of cycling characteristic can be prevented.
摘要翻译：本发明公开了一种闪速存储器件，第一阱和第二阱形成在衬底中，多个存储单元形成在第二阱中并且布置成具有多个位线和字线的阵列。电压分别以时间间隔施加到第一阱和第二阱，使得可以防止存储单元的过度擦除和循环特性的降低。

3. 发明授权

US06282108B1 Voltage control circuit 有权
标题翻译：电压控制电路
公开(公告)号：US06282108B1
公开(公告)日：2001-08-28
申请号：US09722491
申请日：2000-11-28
申请人： Tae Hum Yang
发明人： Tae Hum Yang
IPC分类号： H02M318
CPC分类号： G11C16/30 , H02M3/07
摘要： A voltage control circuit according to the present invention comprises a charge pump for generating a voltage depending on the clock signal inputted thereto; an oscillator for determining the cycle of the clock signal inputted to the charge pump; an adjusting unit for detecting the voltage generated from the charge pump to output an adjusting signal so that the oscillator can vary the cycle of the clock signal inputted to the charge pump.
摘要翻译：根据本发明的电压控制电路包括：电荷泵，用于根据输入的时钟信号产生电压; 用于确定输入到电荷泵的时钟信号的周期的振荡器; 调节单元，用于检测从电荷泵产生的电压以输出调节信号，使得振荡器可以改变输入到电荷泵的时钟信号的周期。

4. 发明授权

US5894438A Method for programming and erasing a memory cell of a flash memory device 失效
标题翻译：用于编程和擦除闪速存储器件的存储单元的方法
公开(公告)号：US5894438A
公开(公告)日：1999-04-13
申请号：US105589
申请日：1998-06-26
申请人： Tae Hum Yang , Young Dong Joo , Joo Young Kim , Jong Bae Jeong , Jong Seuk Lee
发明人： Tae Hum Yang , Young Dong Joo , Joo Young Kim , Jong Bae Jeong , Jong Seuk Lee
IPC分类号： G11C16/04 , G11C16/06 , G11C16/10 , G11C16/14 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/10 , G11C16/14
摘要： The present invention provides a method for programming and erasing a plurality of flash memory cells simultaneously while the power consumptions for those operations are significantly reduced, and the method for programming a memory cell of a flash memory device, wherein the memory cell is formed on a P-well surrounded by an N-well of a semiconductor substrate, including the steps of: applying a negative voltage to a control gate of the memory cell; applying a positive voltage to a drain of the memory cell; applying a positive voltage to the P-well, wherein the voltage is the same as or lower than the voltage applied to the drain; applying a power supply voltage to the N-well; and leaving a source of the memory cell uncoupled, wherein the steps are performed either in sequence or at random.
摘要翻译：本发明提供了一种用于在显着减少用于这些操作的功耗的同时同时编程和擦除多个闪存单元的方法，以及用于对闪存设备的存储单元进行编程的方法，其中存储单元形成在 P阱由半导体衬底的N阱包围，包括以下步骤：向存储单元的控制栅极施加负电压; 对存储单元的漏极施加正电压; 向P阱施加正电压，其中电压与施加到漏极的电压相同或者更低; 向N阱施加电源电压; 并且将所述存储器单元的源离开，其中所述步骤按顺序或随机地执行。

5. 发明授权

US06867109B2 Mask set for compensating a misalignment between patterns and method of compensating a misalignment between patterns using the same 失效
标题翻译：用于补偿图案之间的未对准的掩模组以及使用该图案补偿图案之间的未对准的方法
公开(公告)号：US06867109B2
公开(公告)日：2005-03-15
申请号：US10750832
申请日：2004-01-05
申请人： Soon Won Hong , Tae Hum Yang
发明人： Soon Won Hong , Tae Hum Yang
IPC分类号： G03F1/00 , H01L23/544
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： The present invention discloses a mask set for compensating for a misalignment between the patterns and method of compensating for a misalignment between the patterns. A mask set of the present invention comprises a first mask consisted of a mask substrate on which a main pattern and a plurality of sub-patterns are formed, said sub-patterns formed at a side of the main pattern; a second mask consisted of a mask substrate on which a plurality of hole patterns are formed, the hole patterns corresponded to spaces between the main pattern and the sub-patterns of the first mask, respectively when the first and second mask are overlapped to each other; and a third mask consisted of mask substrate on which a plurality of bar patterns are formed, the bar patterns corresponded to the hole patterns of the second mask, respectively when the second and third mask are overlapped to each other.
摘要翻译：本发明公开了一种用于补偿图案之间的未对准的掩模组和补偿图案之间的未对准的方法。本发明的掩模组包括由形成有主图案和多个子图案的掩模基板构成的第一掩模，所述子图案形成在主图案的一侧; 第二掩模由其上形成有多个孔图案的掩模基板组成，当第一和第二掩模彼此重叠时，孔图案分别对应于主图案和第一掩模的子图案之间的空间 ; 以及第三掩模，其由形成有多个条形图案的掩模基板组成，当第二和第三掩模彼此重叠时，条形图案分别对应于第二掩模的孔图案。

6. 发明授权

US06713883B1 Mask set for compensating a misalignment between patterns 失效
标题翻译：用于补偿图案之间的未对准的掩模集
公开(公告)号：US06713883B1
公开(公告)日：2004-03-30
申请号：US08991261
申请日：1997-12-16
申请人： Soon Won Hong , Tae Hum Yang
发明人： Soon Won Hong , Tae Hum Yang
IPC分类号： H01L23544
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： The present invention discloses a mask set for compensating for a misalignment between the patterns and method of compensating for a misalignment between the patterns. A mask set of the present invention comprises a first mask consisted of a mask substrate on which a main pattern and a plurality of sub-patterns are formed, said sub-patterns formed at a side of the main pattern; a second mask consisted of a mask substrate on which a plurality of hole patterns are formed, the hole patterns corresponded to spaces between the main pattern and the sub-patterns of the first mask, respectively when the first and second mask are overlapped to each other; and a third mask consisted of mask substrate on which a plurality of bar patterns are formed, the bar patterns corresponded to the hole patterns of the second mask, respectively when the second and third mask are overlapped to each other.
摘要翻译：本发明公开了一种用于补偿图案之间的未对准的掩模组和补偿图案之间的未对准的方法。本发明的掩模组包括由形成有主图案和多个子图案的掩模基板构成的第一掩模，所述子图案形成在主图案的一侧; 第二掩模由其上形成有多个孔图案的掩模基板组成，当第一和第二掩模彼此重叠时，孔图案分别对应于主图案和第一掩模的子图案之间的空间 ; 以及第三掩模，其由形成有多个条形图案的掩模基板组成，当第二和第三掩模彼此重叠时，条形图案分别对应于第二掩模的孔图案。

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