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1. 发明授权

US06961274B2 Sense amplifier 失效
标题翻译：感应放大器
公开(公告)号：US06961274B2
公开(公告)日：2005-11-01
申请号：US10601868
申请日：2003-06-24
申请人： Jong Bae Jeong
发明人： Jong Bae Jeong
IPC分类号： G11C16/06 , G11C7/06 , G11C7/12 , G11C7/14 , G11C16/04 , G11C16/28 , G11C7/00
CPC分类号： G11C7/06 , G11C7/12 , G11C7/14 , G11C16/28 , G11C2207/12
摘要： Disclosed is a sense amplifier. The sense amplifier comprises a sensing unit for sensing data stored at a memory cell, a reference voltage generator having a reference cell, for generating a reference voltage, an equalizer that makes same the output of the sensing unit and the output of the reference voltage generator, before a word line of the memory cell is enabled, and is then disabled, and a comparator for comparing the output of the sensing unit and the output of the reference voltage generator. Therefore, the present invention can improve the sensing speed.
摘要翻译：公开了一种读出放大器。感测放大器包括用于感测存储在存储单元中的数据的感测单元，具有用于产生参考电压的参考单元的参考电压发生器，使感测单元的输出和参考电压发生器的输出相同的均衡器在存储单元的字线被使能之前被禁用，以及用于比较感测单元的输出和参考电压发生器的输出的比较器。因此，本发明可以提高感测速度。

2. 发明授权

US06909640B2 Block select circuit in a flash memory device 失效
标题翻译：闪存设备中的块选择电路
公开(公告)号：US06909640B2
公开(公告)日：2005-06-21
申请号：US10464666
申请日：2003-06-19
申请人： Jong Bae Jeong
发明人： Jong Bae Jeong
IPC分类号： G11C16/06 , G11C8/12 , G11C11/34 , G11C16/02 , G11C16/08 , G11C16/12 , G11C29/00
CPC分类号： G11C29/789 , G11C8/12 , G11C16/08 , G11C29/832
摘要： Disclosed is a block select circuit in a flash memory device. The block select circuit comprises a select unit including a flash memory cell that is programmable and erasable by a given voltage condition, for outputting a block select signal depending on address signals and a state of the flash memory cell, a high-voltage pumping unit for outputting a signal to keep a given high voltage according to the block select signal and the clock signal, and a switching unit for applying a given bias to a gate select line, a word line and a source select line of a flash memory cell block according to the output signal of the high-voltage pumping unit. A given voltage is not applied to a fail block by only the operation of programming the flash memory cell of an erase state. Therefore, it is possible to process a fail block even after being packaged.
摘要翻译：公开了闪速存储器件中的块选择电路。块选择电路包括：选择单元，其包括可由可以被给定电压条件编程和擦除的闪存单元，用于根据地址信号和闪速存储单元的状态输出块选择信号;高压抽运单元，用于输出信号以根据块选择信号和时钟信号保持给定的高电压;以及切换单元，用于向闪存单元块的栅选择线，字线和源选择线施加给定偏压，所述切换单元根据到高压泵送单元的输出信号。只有对擦除状态的闪速存储器进行编程的操作，才将给定的电压施加到故障块。因此，即使在封装后也可以处理故障块。

3. 发明授权

US6052305A Erasing circuit for a flash memory device having a triple well structure 有权
标题翻译：具有三重阱结构的闪存器件的擦除电路
公开(公告)号：US6052305A
公开(公告)日：2000-04-18
申请号：US143409
申请日：1998-08-28
申请人： Tae Hum Yang , Joo Young Kim , Young Dong Joo , Jong Bae Jeong , Jong Seuk Lee , Il Hyun Choi , Mun Pyo Hong , Chae Hyun Jung
发明人： Tae Hum Yang , Joo Young Kim , Young Dong Joo , Jong Bae Jeong , Jong Seuk Lee , Il Hyun Choi , Mun Pyo Hong , Chae Hyun Jung
IPC分类号： G11C16/04 , G11C16/16
CPC分类号： G11C16/16
摘要： The present invention discloses a flash memory device, a first well and second well are formed in a substrate, a plurality of memory cell are formed in the second well and arranged in an array having a multiplicity of bit lines and word lines. Voltage is applied to the first well and second well, respectively, with time interval so that an over erasing of the memory cell and lowering of cycling characteristic can be prevented.
摘要翻译：本发明公开了一种闪速存储器件，第一阱和第二阱形成在衬底中，多个存储单元形成在第二阱中并且布置成具有多个位线和字线的阵列。电压分别以时间间隔施加到第一阱和第二阱，使得可以防止存储单元的过度擦除和循环特性的降低。

4. 发明授权

US06950339B2 Circuit for generating trim bit signal in a flash memory device 失效
标题翻译：用于在闪速存储器件中产生微调位信号的电路
公开(公告)号：US06950339B2
公开(公告)日：2005-09-27
申请号：US10462717
申请日：2003-06-17
申请人： Jong Bae Jeong , In Sun Park
发明人： Jong Bae Jeong , In Sun Park
IPC分类号： G11C16/06 , G11C16/02 , G11C16/10 , G11C16/20 , G11C16/26 , G11C29/00
CPC分类号： G11C16/20 , G11C16/10 , G11C16/26 , G11C29/789
摘要： A circuit for generating a trim bit signal in a flash memory device, comprises a control unit selected by a trim bit select signal and including a programmable and erasable cell, and an output unit for outputting a High level signal or a Low level signal through the trim bit signal output terminal depending on the program cell of the control unit.
摘要翻译：一种用于在闪速存储器件中产生微调位信号的电路，包括由微调位选择信号选择并包括可编程和可擦除单元的控制单元，以及用于通过所述可编程和可擦除单元输出高电平信号或低电平信号的输出单元微调位信号输出端子取决于控制单元的编程单元。

5. 发明授权

US06791878B2 Word line decoder in nand type flash memory device 失效
标题翻译： nand型闪存设备中的字线解码器
公开(公告)号：US06791878B2
公开(公告)日：2004-09-14
申请号：US10310033
申请日：2002-12-05
申请人： Jong Bae Jeong
发明人： Jong Bae Jeong
IPC分类号： G11C1604
CPC分类号： G11C8/10 , G11C8/08 , G11C16/08
摘要： A NAND type flash memory device including a word line decoder is disclosed. The word line decoder includes a row decoder, a control unit and a driving unit. The row decoder receives an address of a given memory cell to produce a signal informing whether the memory cell is selected. The control unit outputs a positive or a negative voltage according as the memory cell was selected or not. The driving unit has NMOS transistors for outputting the negative voltage from sources to drains if the positive voltage outputted from the control unit is applied to gates of the NMOS transistors. The NMOS transistors prohibits the negative voltage inputted to the sources from being outputted to the drains if the negative voltage from the control unit is applied to the gates. The negative voltage inputted to the sources is applied to a P well of the NMOS transistors.
摘要翻译：公开了一种包括字线解码器的NAND型闪速存储器件。字线解码器包括行解码器，控制单元和驱动单元。行解码器接收给定存储器单元的地址以产生通知存储器单元是否被选择的信号。根据选择的存储单元，控制单元输出正电压或负电压。如果从控制单元输出的正电压被施加到NMOS晶体管的栅极，则驱动单元具有用于将负电压从源极输出到漏极的NMOS晶体管。如果来自控制单元的负电压施加到栅极，则NMOS晶体管禁止输入到源极的负电压输出到漏极。输入到源极的负电压被施加到NMOS晶体管的P阱。

6. 发明授权

US07668011B2 Serial flash memory device and precharging method thereof 失效
标题翻译：串行闪存装置及其预充电方法
公开(公告)号：US07668011B2
公开(公告)日：2010-02-23
申请号：US12065456
申请日：2006-09-11
申请人： Hun Woo Kye , Jong Bae Jeong , Seung Duck Kim , Sang Yong Lee , Ki Won Kwon , Seung Keun Lee
发明人： Hun Woo Kye , Jong Bae Jeong , Seung Duck Kim , Sang Yong Lee , Ki Won Kwon , Seung Keun Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/28 , G11C7/02 , G11C7/1072 , G11C7/12 , G11C16/24
摘要： Provided herein is a serial flash memory device and precharging method thereof in which a single local bit-line data is sensed in synchronization with a clock. The method includes precharging two or more local bit-lines in synchronization with a first clock; and disprecharging one of the two local bit-lines in synchronization with a second clock and sensing and amplifying data of the other local bit-line. Accordingly, two precharged local bit-lines are not adjacent to each other, thereby eliminating a coupling noise effect. In addition, the time for performing the precharging operation and the sensing operation is easily secured, compared to the prior precharging method in which corresponding local bit-lines are precharged at every clock.
摘要翻译：这里提供了一种串行闪存器件及其预充电方法，其中与时钟同步地感测到单个本地位线数据。该方法包括与第一时钟同步地预充电两个或多个本地位线; 并且与第二时钟同步地分配两个本地位线中的一个，并感测和放大另一个本地位线的数据。因此，两个预充电的局部位线彼此不相邻，从而消除耦合噪声效应。此外，与在每个时钟对相应的本地位线进行预充电的先前预充电方式相比，容易确保执行预充电操作和感测操作的时间。

7. 发明申请

US20080304321A1 Serial Flash Memory Device and Precharging Method Thereof 失效
标题翻译：串行闪存设备及其预充电方法
公开(公告)号：US20080304321A1
公开(公告)日：2008-12-11
申请号：US12065456
申请日：2006-09-11
申请人： Hun Woo Kye , Jong Bae Jeong , Seung Duck Kim , Sang Yong Lee , Ki Won Kwon , Seung Keun Lee
发明人： Hun Woo Kye , Jong Bae Jeong , Seung Duck Kim , Sang Yong Lee , Ki Won Kwon , Seung Keun Lee
IPC分类号： G11C16/02 , G11C16/06 , G11C7/00 , G11C8/00
CPC分类号： G11C16/28 , G11C7/02 , G11C7/1072 , G11C7/12 , G11C16/24
摘要： Provided herein is a serial flash memory device and precharging method thereof in which a single local bit-line data is sensed in synchronization with a clock. The method includes precharging two or more local bit-lines in synchronization with a first clock; and disprecharging one of the two local bit-lines in synchronization with a second clock and sensing and amplifying data of the other local bit-line. Accordingly, two precharged local bit-lines are not adjacent to each other, thereby eliminating a coupling noise effect. In addition, the time for performing the precharging operation and the sensing operation is easily secured, compared to the prior precharging method in which corresponding local bit-lines are precharged at every clock.
摘要翻译：这里提供了一种串行闪存器件及其预充电方法，其中与时钟同步地感测到单个本地位线数据。该方法包括与第一时钟同步地预充电两个或多个本地位线; 并且与第二时钟同步地分配两个本地位线中的一个，并感测和放大另一个本地位线的数据。因此，两个预充电的局部位线彼此不相邻，从而消除耦合噪声效应。此外，与在每个时钟对相应的本地位线进行预充电的先前预充电方式相比，容易确保执行预充电操作和感测操作的时间。

8. 发明授权

US5946233A Flash memory device having word line latch for multi-bit programming 失效
标题翻译：具有用于多位编程的字线锁存器的闪存器件
公开(公告)号：US5946233A
公开(公告)日：1999-08-31
申请号：US99365
申请日：1998-06-18
申请人： Joo Young Kim , Jong Bae Jeong , Jong Seuk Lee , Young Dong Joo
发明人： Joo Young Kim , Jong Bae Jeong , Jong Seuk Lee , Young Dong Joo
IPC分类号： G11C13/00 , G11C16/10 , G11C16/06
CPC分类号： G11C16/10
摘要： This invention relates to a flash memory device capable of performing a multi bit program by sequentially supplying a data stored on a data storage circuit to a word line coupled to a select gate of a memory cell selected by a row decoder when a program bias voltage is applied to a bit line.
摘要翻译：本发明涉及一种闪速存储器件，其能够通过在存储在数据存储电路上的数据上顺序提供耦合到由行解码器所选择的存储单元的选择栅极的字线执行多位程序，当程序偏置电压为应用于位线。

9. 发明授权

US5894438A Method for programming and erasing a memory cell of a flash memory device 失效
标题翻译：用于编程和擦除闪速存储器件的存储单元的方法
公开(公告)号：US5894438A
公开(公告)日：1999-04-13
申请号：US105589
申请日：1998-06-26
申请人： Tae Hum Yang , Young Dong Joo , Joo Young Kim , Jong Bae Jeong , Jong Seuk Lee
发明人： Tae Hum Yang , Young Dong Joo , Joo Young Kim , Jong Bae Jeong , Jong Seuk Lee
IPC分类号： G11C16/04 , G11C16/06 , G11C16/10 , G11C16/14 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/10 , G11C16/14
摘要： The present invention provides a method for programming and erasing a plurality of flash memory cells simultaneously while the power consumptions for those operations are significantly reduced, and the method for programming a memory cell of a flash memory device, wherein the memory cell is formed on a P-well surrounded by an N-well of a semiconductor substrate, including the steps of: applying a negative voltage to a control gate of the memory cell; applying a positive voltage to a drain of the memory cell; applying a positive voltage to the P-well, wherein the voltage is the same as or lower than the voltage applied to the drain; applying a power supply voltage to the N-well; and leaving a source of the memory cell uncoupled, wherein the steps are performed either in sequence or at random.
摘要翻译：本发明提供了一种用于在显着减少用于这些操作的功耗的同时同时编程和擦除多个闪存单元的方法，以及用于对闪存设备的存储单元进行编程的方法，其中存储单元形成在 P阱由半导体衬底的N阱包围，包括以下步骤：向存储单元的控制栅极施加负电压; 对存储单元的漏极施加正电压; 向P阱施加正电压，其中电压与施加到漏极的电压相同或者更低; 向N阱施加电源电压; 并且将所述存储器单元的源离开，其中所述步骤按顺序或随机地执行。

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