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1. 发明授权

US5160429A Piping system for supplying ultra-pure water 失效
标题翻译：用于供应超纯水的管道系统
公开(公告)号：US5160429A
公开(公告)日：1992-11-03
申请号：US635590
申请日：1990-12-31
申请人： Tadahiro Ohmi , Michiya Kawakami , Tadashi Shibata , Masaru Umeda
发明人： Tadahiro Ohmi , Michiya Kawakami , Tadashi Shibata , Masaru Umeda
IPC分类号： B01D61/22 , C02F1/00 , C02F1/32 , C02F1/44 , H01L21/304
CPC分类号： B01D61/22 , C02F1/006 , C02F1/32 , C02F1/444 , Y10S210/90
摘要： The present invention offers a piping system for supplying ultra-pure water, which comprises a circulation tank to store primary pure water from a primary pure water producing unit, a pump for sending the primary pure water from said circulation tank, an outward pipe, one end of which is connected to a final purifying unit to purify primary pure water from said pump to ultra-pure water, a plurality of connection pipes, each end of which is connected to the other end of said outward pipe, a branching pipe connected between the middle of said connection pipe and the ultra-pure water using unit and having a branching valve to adjust the water quantity, and a return pipe connected between the other end of said connection pipe and said circulation tank, characterized in that means for controlling the output of said pump is provided to keep the water pressure at constant level by detecting the water pressure in said outward pipe, thereby supplying a constant quantity of ultra-pure water to the ultra-pure water using unit at all times, and that ultra-pure water of ultra-high purity can be stably supplied by preventing counterflow from the return pipe to the ultra-pure water using unit.
摘要翻译： PCT No.PCT / JP90 / 00648 Sec。 371 1990年12月31日第 102（e）1990年12月31日PCT PCT 1989年6月29日PCT公布。出版物WO90 / 00155 日本1990年1月11日。本发明提供了一种用于提供超纯水的管道系统，其包括循环罐，用于储存来自初级纯水生产单元的初级纯水，用于将来自所述循环的初级纯水罐，一个向外的管，其一端连接到最终净化单元，以将来自所述泵的初级纯水纯化成超纯水;多个连接管，其每个端部连接到所述外部的另一端管，连接在所述连接管的中间和超纯水使用单元之间并具有分流阀以调节水量的分支管;以及连接在所述连接管的另一端和所述循环罐之间的回流管，其特征在于，提供用于控制所述泵的输出的装置，用于通过检测所述外管中的水压来将水压保持在恒定水平，从而提供恒定量的ul 将超纯水用于超纯水使用单位，通过防止从返回管逆流到超纯水使用单元，可以稳定地提供超纯净的超纯水。

2. 发明授权

US5683072A Thin film forming equipment 失效
标题翻译：薄膜成型设备
公开(公告)号：US5683072A
公开(公告)日：1997-11-04
申请号：US508405
申请日：1995-07-31
申请人： Tadahiro Ohmi , Tadashi Shibata , Masaru Umeda
发明人： Tadahiro Ohmi , Tadashi Shibata , Masaru Umeda
IPC分类号： C23C8/14 , C23C14/34 , C23C14/35 , C23C14/56 , C23C16/44 , F16K31/02 , F16K51/02 , H01J37/32 , F16K3/18
CPC分类号： H01J37/32174 , C23C14/34 , C23C14/35 , C23C14/56 , C23C14/564 , C23C16/4404 , C23C8/14 , F16K31/02 , F16K51/02 , H01J37/32082 , H01J2237/186
摘要： A gate valve for a thin film forming apparatus. The gate valve includes two adjoining low-pressure chambers and a wall separating the two chambers. The wall includes an aperture and a thin plate for covering the aperture. The thin plate is movable in a direction substantially parallel to the plate surface. The gate valve further includes a voltage supply for applying a direct current between the thin plate and the wall.
摘要翻译：一种用于薄膜形成装置的闸阀。闸阀包括两个相邻的低压室和分隔两个室的壁。该壁包括孔和用于覆盖孔的薄板。薄板可以在基本上平行于板表面的方向上移动。闸阀还包括用于在薄板和壁之间施加直流电的电压源。

3. 发明授权

US5362672A Method of forming a monocrystalline film having a closed loop step portion on the substrate 失效
标题翻译：在基板上形成具有闭环台阶部分的单晶膜的方法
公开(公告)号：US5362672A
公开(公告)日：1994-11-08
申请号：US465175
申请日：1990-02-01
申请人： Tadahiro Ohmi , Tadashi Shibata , Masaru Umeda
发明人： Tadahiro Ohmi , Tadashi Shibata , Masaru Umeda
IPC分类号： C23C14/06 , H01L21/20 , H01L21/203 , H01L21/336 , H01L21/84
CPC分类号： H01L29/66772 , H01L21/0242 , H01L21/02422 , H01L21/02491 , H01L21/02532 , H01L21/02631 , H01L21/84 , Y10S148/158
摘要： A method of manufacturing a semiconductor device, and particularly a method of forming a monocrystalline film on a substrate. The method includes the step of forming a conductor layer having a step portion on the surface of a substrate. The step portion includes a lateral face which surrounds the lower surface of the step portion to form a closed loop. After the conductor layer has been formed on the surface of the substrate, a monocrystalline film is formed directly on the substrate. Specifically, the film is formed on the lower surface of the step portion, while a DC potential is applied to the conductor layer.
摘要翻译： PCT No.PCT / JP89 / 00599 Sec。 371日期1990年2月1日 102（e）1990年2月1日PCT PCT。1989年6月15日PCT公布。公开号WO89 / 12908 日期：1989年12月28日。一种制造半导体器件的方法，特别是在衬底上形成单晶膜的方法。该方法包括在衬底的表面上形成具有台阶部分的导体层的步骤。台阶部分包括侧面，该侧面围绕台阶部分的下表面以形成闭环。在衬底表面上形成导体层之后，直接在衬底上形成单晶膜。具体地，在台阶部的下表面上形成膜，同时对导体层施加DC电位。

4. 发明授权

US06074538A Thin film forming equipment 失效
标题翻译：薄膜成型设备
公开(公告)号：US06074538A
公开(公告)日：2000-06-13
申请号：US872467
申请日：1997-06-10
申请人： Tadahiro Ohmi , Tadashi Shibata , Masaru Umeda
发明人： Tadahiro Ohmi , Tadashi Shibata , Masaru Umeda
IPC分类号： C23C8/14 , C23C14/34 , C23C14/35 , C23C14/56 , C23C16/44 , F16K31/02 , F16K51/02 , H01J37/32 , C23C14/00
CPC分类号： H01J37/32174 , C23C14/34 , C23C14/35 , C23C14/56 , C23C14/564 , C23C16/4404 , C23C8/14 , F16K31/02 , F16K51/02 , H01J37/32082 , H01J2237/186
摘要： A gate valve for a thin film forming apparatus. The gate valve includes two adjoining low-pressure chambers and a wall separating the two chambers. The wall includes an aperture and a thin plate for covering the aperture. The thin plate is movable in a direction substantially parallel to the plate surface. The gate valve further includes a voltage supply for applying a direct current between the thin plate and the wall.
摘要翻译：一种用于薄膜形成装置的闸阀。闸阀包括两个相邻的低压室和分隔两个室的壁。该壁包括孔和用于覆盖孔的薄板。薄板可以在基本上平行于板表面的方向上移动。闸阀还包括用于在薄板和壁之间施加直流电的电压源。

5. 发明授权

US5854116A Semiconductor apparatus 失效
标题翻译：半导体装置
公开(公告)号：US5854116A
公开(公告)日：1998-12-29
申请号：US422640
申请日：1995-04-14
申请人： Tadahiro Ohmi , Tadashi Shibata , Masaru Umeda
发明人： Tadahiro Ohmi , Tadashi Shibata , Masaru Umeda
IPC分类号： H01L21/285 , H01L21/768 , H01L21/20
CPC分类号： H01L21/2855 , H01L21/76838
摘要： The present invention relates to a semiconductor apparatus adapted to a ultrahigh density integration process. A semiconductor apparatus of the present invention is characterized by including a high concentration impurity layer with the same type of conductivity as that of a semiconductor wafer provided on the back of the semiconductor wafer, and at least one layer of a low resistance electrode provided on said high concentration impurity layer.
摘要翻译：本发明涉及适用于超高密度集成处理的半导体装置。本发明的半导体装置的特征在于包括具有与设置在半导体晶片的背面上的半导体晶片相同类型的导电性的高浓度杂质层，以及至少一层设置在所述半导体晶片上的低电阻电极高浓度杂质层。

6. 发明授权

US5110438A Reduced pressure surface treatment apparatus 失效
标题翻译：减压表面处理设备
公开(公告)号：US5110438A
公开(公告)日：1992-05-05
申请号：US536548
申请日：1990-07-10
申请人： Tadahiro Ohmi , Tadashi Shibata , Masaru Umeda
发明人： Tadahiro Ohmi , Tadashi Shibata , Masaru Umeda
IPC分类号： H01L21/28 , C23C14/22 , C23C14/34 , C23C14/40 , H01J37/32 , H01J37/34 , H01L21/00 , H01L21/285 , H01L29/47 , H01L29/872
CPC分类号： H01L21/67017 , H01J37/32082 , H01J37/32706 , H01J37/34 , H01J2237/32 , H01J2237/3348
摘要： The reduced pressure surface treatment apparatus according the present invention comprises at least one vacuum chamber and an exhaust unit and a gas supply unit connected thereto, and it is characterized in that it is provided with a holder to hold the specimen, means to bombard the specimen with ions without depositing a thin film on said specimen surface, and means to control kinetic energy of said ions to a small value. The reduced pressure surface treatment method of this invention is characterized in that substances adsorbed on the wafer surface or natural oxide film layers are removed by impinging ions on the wafer surface under a vacuum condition.
摘要翻译： PCT No.PCT / JP89 / 00026 Sec。 371日期1990年7月10日 102（e）日1990年7月10日PCT 1990年1月12日提交PCT。根据本发明的减压表面处理装置包括至少一个真空室和排气单元以及与其连接的气体供应单元，其特征在于由于设置有用于保持试样的保持器，用离子轰击试样而不在所述试样表面上沉积薄膜的装置，以及将所述离子的动能控制在较小值的装置。本发明的减压表面处理方法的特征在于，通过在真空条件下在晶片表面上冲击离子来去除吸附在晶片表面或自然氧化物膜层上的物质。

7. 发明授权

US4984060A Semiconductor device wirings with hillocks 失效
标题翻译：半导体器件与小丘配线
公开(公告)号：US4984060A
公开(公告)日：1991-01-08
申请号：US359764
申请日：1989-07-21
申请人： Tadahiro Ohmi , Tadashi Shibata , Masaru Umeda
发明人： Tadahiro Ohmi , Tadashi Shibata , Masaru Umeda
IPC分类号： H01L23/52 , H01L21/3205 , H01L23/522 , H01L23/528
CPC分类号： H01L23/5226 , H01L23/5283 , H01L2924/0002
摘要： A semiconductor device comprises metal wirings with its minimum line width of 1 .mu.m or less and on the surface of said metal wiring there is no hillock which has its height equal to or more than 1/4 of the minimum line width of said metal wiring. The main portion of said metal wiring is formed with pure metal, and is supplied in connection portion between the metal wiring and a semiconductor substrate with a barrier layer for preventing any atoms involved in said metal parts from diffusing into the semiconductor substrate.
摘要翻译： PCT No.PCT / JP88 / 00972 Sec。 371日期：1989年7月21日 102（e）日期1989年7月21日PCT PCT日期为1988年9月24日。一种半导体器件包括其最小线宽为1μm或更小的金属布线，并且在所述金属布线的表面上没有小丘高度等于或大于所述金属布线的最小线宽度的1/4。所述金属布线的主要部分由纯金属形成，并且在金属布线和具有阻挡层的半导体基板之间的连接部分中供应，以防止参与所述金属部件的任何原子扩散到半导体基板中。

8. 发明授权

US06459312B2 Semiconductor integrated circuit, delay-locked loop having the same circuit, self-synchronizing pipeline type system, voltage-controlled oscillator, and phase-locked loop 失效
标题翻译：半导体集成电路，具有相同电路的延迟锁定环路，自同步管线型系统，压控振荡器和锁相环
公开(公告)号：US06459312B2
公开(公告)日：2002-10-01
申请号：US09919926
申请日：2001-08-02
申请人： Katsuhisa Ogawa , Tadahiro Ohmi , Tadashi Shibata
发明人： Katsuhisa Ogawa , Tadahiro Ohmi , Tadashi Shibata
IPC分类号： H03L700
CPC分类号： H03K3/0315 , H03K3/354 , H03K5/133 , H03K2005/00045 , H03L7/0812 , H03L7/0995 , H03L2207/06
摘要： The problem of increase in jitter amounts against increase in delay amounts is solved by a circuit wherein a signal input terminal is connected through a first capacitor to an input terminal of a sense amplifier, a control input terminal is connected through a second capacitor to the input terminal of the sense amplifier, and a common connection point between the input terminal of the sense amplifier and the first and second capacitors is a floating node, and wherein a signal applied through the signal input terminal to the input terminal of the sense amplifier is vertically shifted by a control signal applied to the control input terminal, at least, near a determination threshold of the sense amplifier, thereby controlling a delay amount of an output.
摘要翻译：通过其中信号输入端子通过第一电容器连接到读出放大器的输入端的电路来解决抖动量增加与延迟量增加的问题，控制输入端子通过第二电容器连接到输入端读出放大器的端子和读出放大器的输入端与第一和第二电容器之间的公共连接点是浮动节点，并且其中通过信号输入端施加到读出放大器的输入端的信号是垂直的至少在感测放大器的判定阈值附近，施加到控制输入端子的控制信号移位，从而控制输出的延迟量。

9. 发明授权

US6127852A Semiconductor integrated circuit for parallel signal processing 失效
标题翻译：半导体集成电路并行信号处理
公开(公告)号：US6127852A
公开(公告)日：2000-10-03
申请号：US110014
申请日：1998-07-02
申请人： Katsuhisa Ogawa , Tadahiro Ohmi , Tadashi Shibata
发明人： Katsuhisa Ogawa , Tadahiro Ohmi , Tadashi Shibata
IPC分类号： G01D1/12 , G06G7/12 , G06G7/122 , H01L21/8238 , H01L27/092 , H01L29/78 , H03D1/00
CPC分类号： G06G7/122
摘要： To retrieve analog signals at high precision by a maximum or minimum position detection parallel signal processing circuit, a plurality of circuit units in each of which a gate of a transistor is connected to a signal input terminal through first capacitive means, a common connecting point of the gate and the first capacitive means is connected to one terminal side of second capacitive means, and control means, for fluctuating a voltage on the other terminal side of the second capacitive means so as to further increase or decrease a drain current in correspondence to an increase or decrease in the drain current is connected between the drain and the other terminal side of the second capacitive means are provided, a source of each transistor of the plurality of circuit units is commonly connected and is connected to a constant current source, and the maximum or minimum voltage position detection with respect to a signal voltage which is applied to each signal input terminal is performed by a voltage on the other terminal side of the second capacitive means.
摘要翻译：为了通过最大或最小位置检测并行信号处理电路以高精度检索模拟信号，通过第一电容装置将晶体管的栅极连接到信号输入端的多个电路单元中的多个电路单元，栅极和第一电容装置连接到第二电容装置的一个端子侧，以及控制装置，用于使第二电容装置的另一个端子侧的电压波动，以进一步增加或减少对应于在第二电容装置的漏极和另一个端子侧之间连接漏极电流的增加或减少，多个电路单元中的每个晶体管的源极共同连接并连接到恒定电流源，并且执行相对于施加到每个信号输入端子的信号电压的最大或最小电压位置检测通过第二电容装置的另一个端子侧的电压。

10. 发明授权

US6115725A Semiconductor arithmetic apparatus 失效
标题翻译：半导体运算装置
公开(公告)号：US6115725A
公开(公告)日：2000-09-05
申请号：US14644
申请日：1998-01-28
申请人： Tadashi Shibata , Tadahiro Ohmi , Akira Nataka , Tatsuo Morimoto , Masahiro Konda
发明人： Tadashi Shibata , Tadahiro Ohmi , Akira Nataka , Tatsuo Morimoto , Masahiro Konda
IPC分类号： G06T9/00 , H03M7/30 , G06F7/00 , H04N7/12
CPC分类号： H03M7/3082 , G06T9/008 , H04N19/94
摘要： The real time compression of moving images employing vector quantization is realized using simple hardware and with an optimal compression ratio with respect to the communication line capacity employed. In the operating system, which is provided with a first mechanism (202), comprising a plurality of groups of numerical values, a second mechanism (201), a first circuit (206), a second circuit (206), and a third circuit (210), the second circuit comprises a plurality of fourth circuits divided into two or more groups (210-213, 219, and 301), the fourth circuits have a plurality of input terminals and at least one output terminal, and a mechanism is provided having a structure wherein various signals expressing degrees of similarity are inputted into the plurality of input terminals, only that signal having the largest degree of similarity among the variety of signals expressing degrees of similarity which are inputted is outputted from the output terminal, and the output signal of a predetermined first group among the two or more groups is inputted into an input terminal of a second group, whereby only one first vector having the largest degree of similarity is selected.
摘要翻译：使用矢量量化的运动图像的实时压缩是使用简单的硬件和相对于所采用的通信线路容量的最佳压缩比来实现的。在具有第一机构（202）的操作系统中，包括多组数值，第二机构（201），第一电路（206），第二电路（206）和第三电路（210），所述第二电路包括分成两组或更多组（210-213,219和301）的多个第四电路，所述第四电路具有多个输入端子和至少一个输出端子，并且机构是具有这样的结构，其中表示相似度的各种信号被输入到多个输入端，只有表示输入的相似度的各种信号之间具有最大相似程度的信号从输出端输出，将两个以上组中的预定第一组的输出信号输入到第二组的输入端，由此仅选择具有最大相似度的一个第一矢量。

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