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    • 10. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US06785172B2
    • 2004-08-31
    • US10325931
    • 2002-12-23
    • Yoshiki Kobayashi
    • Yoshiki Kobayashi
    • G11C700
    • G11C29/32G11C2029/3202G11C2207/104
    • In a semiconductor memory device according to the present invention, which allows a memory cell array unit and a memory circuit internal logic unit to be tested independently of each other, a first test circuit unit TCi1 to which an address signal a″, a scan-in signal SIN, a scan select signal SS and a shift clock signal SCLK are input, outputs an address signal a′″ and a scan-out signal SiOUT1. The address signal a′″ is input to the memory cell array unit MCA and a column selector CS, whereas the scan-out signal SiOUT1 is input to a second test circuit unit TCi2. The second test circuit unit TCi2, to which the scan-out signal SiOUT1, the scan select signal SS, a write control signal WCTRL and a scan clock signal SCLK are input, outputs at a scan-out signal SOUT. The first test circuit unit and the second test circuit unit each achieve a parallel/serial conversion function.
    • 在根据本发明的半导体存储器件中,允许独立地测试存储单元阵列单元和存储器电路内部逻辑单元的第一测试电路单元TCi1,地址信号a“,扫描 输入信号SIN,扫描选择信号SS和移位时钟信号SCLK,输出地址信号a“和扫描输出信号SiOUT1。 地址信号a“”被输入到存储单元阵列单元MCA和列选择器CS,而扫描输出信号SiOUT1被输入到第二测试电路单元TCi2。 扫描输出信号SiOUT1,扫描选择信号SS,写控制信号WCTRL和扫描时钟信号SCLK被输入的第二测试电路单元TCi2以扫描输出信号SOUT输出。 第一测试电路单元和第二测试电路单元各自实现并行/串行转换功能。