会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 5. 发明申请
    • Push-pull amplifier circuit and operational amplifier circuit using the same
    • 推挽放大电路和运算放大器电路使用相同
    • US20110050342A1
    • 2011-03-03
    • US12805265
    • 2010-07-21
    • Tachio Yuasa
    • Tachio Yuasa
    • H03F3/45H03F3/26
    • H03F3/3022H03F3/45183H03F2203/45632H03F2203/45674
    • A push-pull amplifier including first to third current paths. The first current path includes first transistor allowing first current to flow through the first current path according to input signal. The second current path includes second transistor allowing second current having opposite phase to the first current to flow through the second current path according to the first current; first resistor; and third transistor connected to one end of the first resistor and having control terminal connected to the other end of the first resistor. The third current path includes output terminal; fourth transistor allowing current having the same phase as the first current to flow through the third current path according to the input signal; and fifth transistor allowing current having the same phase as the second current to flow through the third current path according to voltage of first node between the first resistor and the third transistor.
    • 包括第一至第三电流路径的推挽放大器。 第一电流路径包括允许第一电流根据输入信号流过第一电流路径的第一晶体管。 第二电流路径包括允许与第一电流相反相位的第二电流根据第一电流流过第二电流路径的第二晶体管; 第一电阻; 所述第三晶体管连接到所述第一电阻器的一端并且具有连接到所述第一电阻器的另一端的控制端子。 第三电流路径包括输出端子; 第四晶体管,其允许具有与所述第一电流相同相位的电流根据所述输入信号流过所述第三电流路径; 以及第五晶体管,其允许具有与第二电流相同相位的电流根据第一电阻器和第三晶体管之间的第一节点的电压流过第三电流路径。
    • 6. 发明申请
    • Amplifier circuit with resistive current limitter
    • 具有电阻电流限制器的放大器电路
    • US20100271132A1
    • 2010-10-28
    • US12662514
    • 2010-04-21
    • Tachio Yuasa
    • Tachio Yuasa
    • H03F3/16
    • H03F3/345
    • An amplifier circuit includes first transistor of first conductivity type having source connected to first power supply, while having gate connected to input terminal and drain connected to output terminal; transistor of second conductivity type having source connected to second power supply and drain connected to the output terminal; second transistor of the first conductivity type whose source and gate are connected to the source and gate of the first transistor of the first conductivity type, respectively; resistor whose one end connected to drain of the second transistor of the first conductivity type, and an output control circuit; current input terminal connected to the opposite end of the resistor; and voltage output terminal connected to the gate of the transistor of the second conductivity type. The output control circuit controls the gate voltage of the transistor of the second conductivity type based on the input current of the current input terminal.
    • 放大器电路包括:第一导电类型的第一晶体管,其源极连接到第一电源,同时具有连接到输入端子的栅极和连接到输出端子的漏极; 具有源极的第二导电类型的晶体管连接到连接到输出端子的第二电源和漏极; 第一导电类型的第二晶体管,其源极和栅极分别连接到第一导电类型的第一晶体管的源极和栅极; 电阻器的一端连接到第一导电类型的第二晶体管的漏极,以及输出控制电路; 电流输入端连接到电阻的另一端; 并且电压输出端子连接到第二导电类型的晶体管的栅极。 输出控制电路基于电流输入端子的输入电流来控制第二导电类型的晶体管的栅极电压。
    • 7. 发明申请
    • Differential amplifier with symmetric circuit topology
    • 具有对称电路拓扑的差分放大器
    • US20100007417A1
    • 2010-01-14
    • US12314979
    • 2008-12-19
    • Tachio Yuasa
    • Tachio Yuasa
    • H03F3/45
    • H03F3/45219H03F2203/45212H03F2203/45646H03F2203/45681
    • A differential amplifier circuit is provided with a first input stage including a transistor pair of a first conductivity type, of which transistor pair receives differential input signals; a first output stage connected to the first input stage; a second input stage including a transistor pair of a second conductivity type different from the first conductivity type, of which transistor pair receives the differential input signals; a second output stage connected to the second input stage; and an output terminal. The second output stage is structured with a circuit topology in which transistors of the first conductivity type in the first output stage are replaced with transistors of the second conductivity type, transistors of the second conductivity type in the first output stage are replaced with transistors of the first conductivity type, ground terminals in the first output stage are replaced with power supply terminals, and power supply terminals in the first output stage are replaced with ground terminals. The output terminal is commonly connected to outputs of the first and second output stages.
    • 差分放大器电路设置有包括第一导电类型的晶体管对的第一输入级,其中晶体管对接收差分输入信号; 连接到第一输入级的第一输出级; 第二输入级,其包括不同于第一导电类型的第二导电类型的晶体管对,其中晶体管对接收差分输入信号; 连接到第二输入级的第二输出级; 和输出端子。 第二输出级由电路拓扑构成,其中第一输出级中的第一导电类型的晶体管被​​第二导电类型的晶体管代替,第一输出级中的第二导电类型的晶体管被​​替换为 第一导电类型,第一输出级中的接地端子被替换为电源端子,并且第一输出级中的电源端子被替换为接地端子。 输出端子通常连接到第一和第二输出级的输出。
    • 9. 发明授权
    • Digital-to-analog converter for reducing occupied area thereof
    • 用于减少占用面积的数模转换器
    • US5568147A
    • 1996-10-22
    • US334343
    • 1994-11-02
    • Atsushi MatsudaTachio Yuasa
    • Atsushi MatsudaTachio Yuasa
    • H03M1/68H03M1/74H03M1/76H03M1/80
    • H03M1/687H03M1/765H03M1/808
    • A D/A converter has a first partial circuit, and second and third partial circuits connected with said first partial circuit. The first partial circuit has a first row of K resistors of the same resistance value and groups of switches provided for the resistors, to select "K-1" resistors among said K resistors and connect said selected resistors in series with said second and third partial circuits. The second partial circuit has a second row of L resistors, a first group of switches connected in series with said resistors, respectively, and a second group of switches connected in parallel with said series-connected second row of resistors and said first group of switches, respectively. The third partial circuit has a third row of L resistors, a third group of switches connected in series with said resistors, respectively, and a fourth group of switches connected in parallel with said series-connected third row of resistors and said third group of switches, respectively. Therefore, the D/A converter can reduces an occupied area thereof, and increases the number of D/A converter chips to be fabricated on a wafer, to thereby reduce the costs of the D/A converters.
    • D / A转换器具有第一部分电路,以及与所述第一部分电路连接的第二和第三部分电路。 第一部分电路具有相同电阻值的第一排K电阻器和为电阻器提供的开关组,以在所述K个电阻器中选择“K-1”电阻器,并将所选择的电阻器与所述第二和第三部分串联连接 电路。 第二部分电路具有第二排L电阻器,分别与所述电阻器串联连接的第一组开关,以及与所述串联连接的第二排电阻器和所述第一组开关并联连接的第二组开关 , 分别。 第三部分电路具有第三排L电阻器,分别与所述电阻器串联的第三组开关,以及与所述串联连接的第三排电阻器和所述第三组开关并联连接的第四组开关 , 分别。 因此,D / A转换器可以减少其占用面积,并且增加要在晶片上制造的D / A转换器芯片的数量,从而降低D / A转换器的成本。
    • 10. 发明授权
    • Reference current generating circuit
    • 参考电流发生电路
    • US08441312B2
    • 2013-05-14
    • US13044316
    • 2011-03-09
    • Tachio Yuasa
    • Tachio Yuasa
    • G05F1/10
    • G05F3/24
    • A reference current generating circuit has: first and second current mirror circuits and first and second output terminals. The first current mirror circuit has: a first transistor of a first polarity being an input-side transistor; and a first resistor connected between a gate of the first transistor and a power supply terminal. The second current mirror circuit has a second transistor of a second polarity being an input-side transistor. An output node of the first current mirror circuit is connected to an input node of the second current mirror circuit, and an input node of the first current mirror circuit is connected to an output node of the second current mirror circuit. A control voltage applied to the gate of the first transistor is output from the first output terminal. A control voltage applied to a gate of the second transistor is output from the second output terminal.
    • 参考电流产生电路具有:第一和第二电流镜电路以及第一和第二输出端。 第一电流镜电路具有:第一极性的第一晶体管是输入侧晶体管; 以及连接在第一晶体管的栅极和电源端子之间的第一电阻器。 第二电流镜电路具有作为输入侧晶体管的第二极性的第二晶体管。 第一电流镜电路的输出节点连接到第二电流镜电路的输入节点,第一电流镜电路的输入节点连接到第二电流镜电路的输出节点。 从第一输出端子输出施加到第一晶体管的栅极的控制电压。 从第二输出端子输出施加到第二晶体管的栅极的控制电压。