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1. 发明授权

US06831350B1 Semiconductor structure with different lattice constant materials and method for forming the same 有权
标题翻译：具有不同晶格常数材料的半导体结构及其形成方法
公开(公告)号：US06831350B1
公开(公告)日：2004-12-14
申请号：US10677844
申请日：2003-10-02
申请人： Chun-Li Liu , Alexander L. Barr , John M. Grant , Bich-Yen Nguyen , Marius K. Orlowski , Tab A. Stephens , Ted R. White , Shawn G. Thomas
发明人： Chun-Li Liu , Alexander L. Barr , John M. Grant , Bich-Yen Nguyen , Marius K. Orlowski , Tab A. Stephens , Ted R. White , Shawn G. Thomas
IPC分类号： H01L2930
CPC分类号： H01L29/1054 , H01L21/0237 , H01L21/02381 , H01L21/0245 , H01L21/02507 , H01L21/02532 , H01L21/02639 , H01L21/02647 , H01L29/04 , H01L29/665 , H01L29/7833
摘要： A semiconductor structure includes a substrate comprising a first relaxed semiconductor material with a first lattice constant. A semiconductor device layer overlies the substrate, wherein the semiconductor device layer includes a second relaxed semiconductor material with a second lattice constant different from the first lattice constant. In addition, a dielectric layer is interposed between the substrate and the semiconductor device layer, wherein the dielectric layer includes a programmed transition zone disposed within the dielectric layer for transitioning between the first lattice constant and the second lattice constant. The programmed transition zone includes a plurality of layers, adjoining ones of the plurality of layers having different lattice constants with one of the adjoining ones having a first thickness exceeding a first critical thickness required to form defects and another of the adjoining ones having a second thickness not exceeding a second critical thickness. Each adjoining layer of the plurality of layers forms an interface for promoting defects in the transition zone to migrate to and terminate on an edge of the programmed transition zone. A method of making the same is also disclosed.
摘要翻译：半导体结构包括具有第一晶格常数的第一松弛半导体材料的衬底。半导体器件层覆盖在衬底上，其中半导体器件层包括具有不同于第一晶格常数的第二晶格常数的第二松弛半导体材料。此外，介电层介于基板和半导体器件层之间，其中介电层包括设置在电介质层内的编程过渡区，用于在第一晶格常数和第二晶格常数之间转变。编程的过渡区域包括多个层，多个层中相邻的层具有不同的晶格常数，其中相邻的层之一具有超过形成缺陷所需的第一临界厚度的第一厚度，而另一层具有第二厚度不超过第二临界厚度。多个层中的每个相邻层形成用于促进过渡区中的缺陷迁移到并终止于编程的过渡区的边缘的界面。还公开了制备该方法的方法。

2. 发明授权

US07029980B2 Method of manufacturing SOI template layer 有权
标题翻译：制造SOI模板层的方法
公开(公告)号：US07029980B2
公开(公告)日：2006-04-18
申请号：US10670928
申请日：2003-09-25
申请人： Chun-Li Liu , Marius K. Orlowski , Matthew W. Stoker , Philip J. Tobin , Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White
发明人： Chun-Li Liu , Marius K. Orlowski , Matthew W. Stoker , Philip J. Tobin , Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White
IPC分类号： H01L21/331
CPC分类号： H01L29/161 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/1054 , Y10S438/933
摘要： A vacancy injecting process for injecting vacancies in template layer material of an SOI substrate. The template layer material has a crystalline structure that includes, in some embodiments, both germanium and silicon atoms. A strained silicon layer is then epitaxially grown on the template layer material with the beneficial effects that straining has on electron and hole mobility. The vacancy injecting process is performed to inject vacancies and germanium atoms into the crystalline structure wherein germanium atoms recombine with the vacancies. One embodiment, a nitridation process is performed to grow a nitride layer on the template layer material and consume silicon in a way that injects vacancies in the crystalline structure while also allowing germanium atoms to recombine with the vacancies. Other examples of a vacancy injecting processes include silicidation processes, oxynitridation processes, oxidation processes with a chloride bearing gas, or inert gas post bake processes subsequent to an oxidation process.
摘要翻译：用于在SOI衬底的模板层材料中注入空位的空位注入工艺。模板层材料具有在一些实施方案中包括锗和硅原子的晶体结构。然后在模板层材料上外延生长应变硅层，具有应力对电子和空穴迁移率的有益效果。进行空位注入处理以将空位和锗原子注入晶格结构中，其中锗原子与空位重新组合。一个实施方案中，进行氮化处理以在模板层材料上生长氮化物层，并以注入晶体结构中的空位并且还允许锗原子与空位复合的方式消耗硅。空位注入方法的其它实例包括硅化工艺，氧氮化工艺，含氯化物气体的氧化工艺或氧化工艺之后的惰性气体后烘烤工艺。

3. 发明授权

US07241647B2 Graded semiconductor layer 有权
标题翻译：分级半导体层
公开(公告)号：US07241647B2
公开(公告)日：2007-07-10
申请号：US10919952
申请日：2004-08-17
申请人： Mariam G. Sadaka , Shawn G. Thomas , Ted R. White , Chun-Li Liu , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean
发明人： Mariam G. Sadaka , Shawn G. Thomas , Ted R. White , Chun-Li Liu , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean
IPC分类号： H01L21/00
CPC分类号： H01L29/78687 , H01L29/1054 , H01L29/6659 , H01L29/66742
摘要： A process for forming a semiconductor device. The process includes forming a template layer for forming a layer of strained silicon. In one example a layer of graded silicon germanium is formed where the germanium is at a higher concentration at the lower portion and at a lower concentration at a top portion. When subject to a condensation process, the germanium of the top portion of the layer diffuses to a remaining portion of the silicon germanium layer. Because the silicon germanium layer has a higher concentration of germanium at lower portions, germanium pile up after condensation may be reduced at the upper portion of the remaining portion of the silicon germanium layer.
摘要翻译：一种形成半导体器件的方法。该方法包括形成用于形成应变硅层的模板层。在一个示例中，形成梯度硅锗层，其中锗在下部处具有较高的浓度，在顶部处的浓度较低。当进行冷凝处理时，层的顶部的锗扩散到硅锗层的剩余部分。由于硅锗层在下部具有较高的锗浓度，所以在硅锗层的剩余部分的上部可以减少在冷凝后堆积的锗。

4. 发明授权

US07056778B2 Semiconductor layer formation 失效
标题翻译：半导体层形成
公开(公告)号：US07056778B2
公开(公告)日：2006-06-06
申请号：US10919784
申请日：2004-08-17
申请人： Chun-Li Liu , Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White , Qianghua Xie
发明人： Chun-Li Liu , Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White , Qianghua Xie
IPC分类号： H01L21/338
CPC分类号： H01L29/161 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/1054 , Y10S438/933
摘要： A process for forming strained semiconductor layers. The process include flowing a chlorine bearing gas (e.g. hydrogen chloride, chlorine, carbon tetrachloride, and trichloroethane) over the wafer while heating the wafer. In one example, the chorine bearing gas is flowed during a condensation process on a semiconductor layer that is used as a template layer for forming a strain semiconductor layer (e.g. strain silicon). In other examples, the chlorine bearing gas is flowed during a post bake of the wafer after the condensation operation.
摘要翻译：一种形成应变半导体层的工艺。该方法包括在加热晶片的同时使含氯气体（例如氯化氢，氯气，四氯化碳和三氯乙烷）流过晶片。在一个实例中，在用作形成应变半导体层（例如应变硅）的模板层的半导体层上的冷凝过程中，含有轴承气体流动。在其他实例中，在冷凝操作之后，在晶片的后烘烤期间，含氯气体流动。

5. 发明授权

US07226833B2 Semiconductor device structure and method therefor 有权
标题翻译：半导体器件结构及其方法
公开(公告)号：US07226833B2
公开(公告)日：2007-06-05
申请号：US10977423
申请日：2004-10-29
申请人： Ted R. White , Alexander L. Barr , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean
发明人： Ted R. White , Alexander L. Barr , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean
IPC分类号： H01L21/8234
CPC分类号： H01L29/78696 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/66772
摘要： Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.
摘要翻译：在不同的晶体取向上制作了两种不同的晶体管类型，其中两者都形成在SOI上。衬底具有晶体取向之一的底层半导体层和另一晶体取向的上覆层。底层具有暴露在其上的部分外延生长保持下面的半导体层的晶体结构的氧掺杂半导体层。然后在氧掺杂半导体层上外延生长半导体层。在高温下的氧化步骤使得氧化物掺杂区域分离成氧化物和半导体区域。然后将氧化物区域用作SOI结构中的绝缘层，并且剩下的上覆半导体层具有与下面的半导体层相同的晶体取向。不同类型的晶体管形成在不同的结晶取向上。

6. 发明授权

US07781840B2 Semiconductor device structure 有权
标题翻译：半导体器件结构
公开(公告)号：US07781840B2
公开(公告)日：2010-08-24
申请号：US11742955
申请日：2007-05-01
申请人： Ted R. White , Alexander L. Barr , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean
发明人： Ted R. White , Alexander L. Barr , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean
IPC分类号： H01L29/786
CPC分类号： H01L29/78696 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/66772
摘要： Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.
摘要翻译：在不同的晶体取向上制作了两种不同的晶体管类型，其中两者都形成在SOI上。衬底具有晶体取向之一的底层半导体层和另一晶体取向的上覆层。底层具有暴露在其上的部分外延生长保持下面的半导体层的晶体结构的氧掺杂半导体层。然后在氧掺杂半导体层上外延生长半导体层。在高温下的氧化步骤使得氧化物掺杂区域分离成氧化物和半导体区域。然后将氧化物区域用作SOI结构中的绝缘层，并且剩下的上覆半导体层具有与下面的半导体层相同的晶体取向。不同类型的晶体管形成在不同的结晶取向上。

7. 发明授权

US07037795B1 Low RC product transistors in SOI semiconductor process 有权
标题翻译： SOI半导体工艺中的低RC产品晶体管
公开(公告)号：US07037795B1
公开(公告)日：2006-05-02
申请号：US10965964
申请日：2004-10-15
申请人： Alexander L. Barr , Olubunmi O. Adetutu , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean , Ted R. White
发明人： Alexander L. Barr , Olubunmi O. Adetutu , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean , Ted R. White
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/66636 , H01L29/78618
摘要： A semiconductor fabrication process includes forming a transistor gate overlying an SOI wafer having a semiconductor top layer over a buried oxide layer (BOX) over a semiconductor substrate. Source/drain trenches, disposed on either side of the gate, are etched into the BOX layer. Source/drain structures are formed within the trenches. A depth of the source/drain structures is greater than the thickness of the top silicon layer and an upper surface of the source/drain structures coincides approximately with the transistor channel whereby vertical overlap between the source/drain structures and the gate is negligible. The trenches preferably extend through the BOX layer to expose a portion of the silicon substrate. The source/drain structures are preferably formed epitaxially and possibly in two stages including an oxygen rich stage and an oxygen free stage. A thermally anneal between the two epitaxial stages will form an isolation dielectric between the source/drain structure and the substrate.
摘要翻译：半导体制造工艺包括在半导体衬底上的掩埋氧化物层（BOX）上形成半导体顶层的SOI晶片的晶体管栅极。设置在栅极两侧的源极/漏极沟槽被蚀刻到BOX层中。源极/漏极结构形成在沟槽内。源极/漏极结构的深度大于顶部硅层的厚度，并且源极/漏极结构的上表面大致与晶体管沟道重合，源极/漏极结构与栅极之间的垂直重叠可忽略不计。沟槽优选地延伸穿过BOX层以暴露硅衬底的一部分。源极/漏极结构优选外延地形成，并且可能包括富氧阶段和无氧阶段的两个阶段。两个外延级之间的热退火将在源极/漏极结构和衬底之间形成隔离电介质。

8. 发明授权

US07282402B2 Method of making a dual strained channel semiconductor device 有权
标题翻译：制造双应变通道半导体器件的方法
公开(公告)号：US07282402B2
公开(公告)日：2007-10-16
申请号：US11093801
申请日：2005-03-30
申请人： Mariam G. Sadaka , Alexander L. Barr , Dejan Jovanovic , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White
发明人： Mariam G. Sadaka , Alexander L. Barr , Dejan Jovanovic , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.
摘要翻译：根据本公开的实施例，制造双应变通道半导体器件的过程包括将应变Si和压缩SiGe与沟槽隔离相集成，以实现同时的NMOS和PMOS性能增强。如本文所述，NMOS和PMOS的集成可以以几种方式实现，以实现与浅沟槽隔离兼容的NMOS和PMOS沟道。

9. 发明授权

US07208357B2 Template layer formation 有权
标题翻译：模板层形成
公开(公告)号：US07208357B2
公开(公告)日：2007-04-24
申请号：US10919922
申请日：2004-08-17
申请人： Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Ted R. White
发明人： Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Ted R. White
IPC分类号： H01L21/00 , H01L21/20 , H01L21/425
CPC分类号： H01L29/161 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/1054 , Y10S438/933
摘要： A process for forming a strained semiconductor layer. The process includes implanting ions into a semiconductor layer prior to performing a condensation process on the layer. The ions assist in diffusion of atoms (e.g. germanium) in the semiconductor layer and to increase the relaxation of the semiconductor layer. After the condensation process, the layer can be used as a template layer for forming a strained semiconductor layer.
摘要翻译：一种形成应变半导体层的工艺。该方法包括在层之前进行冷凝过程之前将离子注入到半导体层中。离子有助于半导体层中的原子（例如锗）的扩散并增加半导体层的松弛。在冷凝过程之后，该层可用作形成应变半导体层的模板层。

10. 发明授权

US07811382B2 Method for forming a semiconductor structure having a strained silicon layer 有权
标题翻译：用于形成具有应变硅层的半导体结构的方法
公开(公告)号：US07811382B2
公开(公告)日：2010-10-12
申请号：US11421009
申请日：2006-05-30
申请人： Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Ted R. White
发明人： Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Ted R. White
IPC分类号： C30B21/02
CPC分类号： C30B29/52 , C30B25/02 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/0262 , H01L21/76254
摘要： A wafer having a silicon layer that is strained is used to form transistors. The silicon layer is formed by first forming a silicon germanium (SiGe) layer of at least 30 percent germanium that has relaxed strain on a donor wafer. A thin silicon layer is epitaxially grown to have tensile strain on the relaxed SiGe layer. The amount tensile strain is related to the germanium concentration. A high temperature oxide (HTO) layer is formed on the thin silicon layer by reacting dichlorosilane and nitrous oxide at a temperature of preferably between 800 and 850 degrees Celsius. A handle wafer is provided with a supporting substrate and an oxide layer that is then bonded to the HTO layer. The HTO layer, being high density, is able to hold the tensile strain of the thin silicon layer. The relaxed SiGe layer is cleaved then etched away to expose the thin silicon layer. A low temperature silicon layer is then epitaxially grown with tensile strain, correlated to the tensile strain of the thin silicon layer, on the thin silicon layer using trisilane at a temperature preferably not in excess of 500 degrees Celsius. The resulting tensile strain, correlated to the strain of the thin silicon layer, is thus also correlated to the germanium concentration of the relaxed SiGe layer. The thickness of the low temperature silicon layer, using the trisilane at low temperature, is significantly greater than what would normally be expected for a silicon layer of that tensile strain.
摘要翻译：具有应变的硅层的晶片用于形成晶体管。通过首先在施主晶片上形成具有松弛应变的至少30％的锗的锗锗（SiGe）层来形成硅层。外延生长薄硅层以在松弛的SiGe层上具有拉伸应变。拉伸应变量与锗浓度有关。优选在800至850摄氏度之间的温度下，通过使二氯硅烷和一氧化二氮反应，在薄硅层上形成高温氧化物（HTO）层。手柄晶片设置有支撑基板和氧化物层，然后将其结合到HTO层。高密度的HTO层能够保持薄硅层的拉伸应变。松弛的SiGe层被切割，然后蚀刻掉以露出薄的硅层。然后在优选不超过500摄氏度的温度下使用丙硅烷在薄硅层上外延生长与低硅薄层的拉伸应变相关的低温硅层。因此，与薄硅层的应变相关的所得拉伸应变也与弛豫SiGe层的锗浓度相关。在低温下使用丙硅烷的低温硅层的厚度明显大于该拉伸应变的硅层通常预期的厚度。

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