专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20200074713A1 POSITION-BASED RENDERING APPARATUS AND METHOD FOR MULTI-DIE/GPU GRAPHICS PROCESSING 审中-公开
公开(公告)号：US20200074713A1
公开(公告)日：2020-03-05
申请号：US16116158
申请日：2018-08-29
申请人： TRAVIS SCHLUESSLER , ZACK WATERS , MICHAEL APODACA , DANIEL JOHNSTON , JASON SURPRISE , PRASOONKUMAR SURTI , SUBRAMANIAM MAIYURAN , PETER DOYLE , SAURABH SHARMA , ANKUR SHAH , MURALI RAMADOSS
发明人： TRAVIS SCHLUESSLER , ZACK WATERS , MICHAEL APODACA , DANIEL JOHNSTON , JASON SURPRISE , PRASOONKUMAR SURTI , SUBRAMANIAM MAIYURAN , PETER DOYLE , SAURABH SHARMA , ANKUR SHAH , MURALI RAMADOSS
IPC分类号： G06T15/00 , G06T15/80 , G06T15/40
摘要： Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

2. 发明申请

US20140320509A1 TECHNIQUES FOR GRAPHICS DATA PREFETCHING 有权
标题翻译：图形数据预处理技术
公开(公告)号：US20140320509A1
公开(公告)日：2014-10-30
申请号：US13870924
申请日：2013-04-25
申请人： WEI-YU CHEN , GUEI-YUAN LUEH , SUBRAMANIAM MAIYURAN
发明人： WEI-YU CHEN , GUEI-YUAN LUEH , SUBRAMANIAM MAIYURAN
IPC分类号： G06T1/20
CPC分类号： G06T1/20
摘要： Various embodiments are generally directed to techniques to prefetch pixel data of one or more pixels adjacent to a pixel for which pixel data is retrieved where the prefetched pixel data may be stored in noncontiguous storage locations. A device comprising a processor component and a hint generation component executed by the processor component to embed a prefetch hint in an executable read instruction, the executable read instruction to retrieve pixel data of a specified pixel and the prefetch hint to retrieve pixel data of an adjacent pixel that is geometrically adjacent to the specified pixel. Other embodiments are described and claimed.
摘要翻译：各种实施例通常涉及用于预取与检索像素数据的像素相邻的一个或多个像素的像素数据的技术，其中预取像素数据可存储在非连续的存储位置中。一种设备，包括由处理器组件执行的处理器组件和提示生成组件，以将预取提示嵌入到可执行读取指令中，该可执行读取指令检索指定像素的像素数据和预取提示以检索邻近的像素数据与指定像素几何相邻的像素。描述和要求保护其他实施例。

3. 发明申请

US20170091893A1 METHOD AND APPARATUS FOR ADAPTIVE PIXEL HASHING FOR GRAPHICS PROCESSORS 有权
公开(公告)号：US20170091893A1
公开(公告)日：2017-03-30
申请号：US14866437
申请日：2015-09-25
申请人： KALYAN K. BHIRAVABHATLA , SUBRAMANIAM MAIYURAN , JORGE F. GARCIA PABON
发明人： KALYAN K. BHIRAVABHATLA , SUBRAMANIAM MAIYURAN , JORGE F. GARCIA PABON
IPC分类号： G06T1/20 , G06T1/60
CPC分类号： G06T1/20 , G06F11/1453 , G06F17/3033 , G06T1/60
摘要： An apparatus and method for adaptive pixel hashing. For example, one embodiment of a method comprises: determining X and Y coordinates for a pixel block to be processed; performing a first lookup in a first data structure to identify a second data structure; performing a second lookup in the second data structure using the X and Y coordinates for the pixel block to identify a third data structure; performing a third lookup in a third data structure indexed based on the X and Y coordinates of the pixel block, the third lookup identifying an entry in the third data structure corresponding to the X and Y coordinates of the pixel block; reading information from the entry identifying an execution cluster to process the pixel block; and processing the pixel block by the execution cluster.

4. 发明申请

US20150379664A1 ACCELERATED SINGLE PLANE CLIPPING OF POLYGONS IN GRAPHICS PROCESSING 审中-公开
标题翻译：图形处理中多边形的加速单平面剪切
公开(公告)号：US20150379664A1
公开(公告)日：2015-12-31
申请号：US14316895
申请日：2014-06-27
申请人： KALYAN K. BHIRAVABHATLA , PETER L. DOYLE , SUBRAMANIAM MAIYURAN
发明人： KALYAN K. BHIRAVABHATLA , PETER L. DOYLE , SUBRAMANIAM MAIYURAN
IPC分类号： G06T1/20 , G06T17/10
CPC分类号： G06T15/30
摘要： Methods and hardware may process single plane clipping operations using a pipeline specialized for single plane clipping. A second pipeline may be provided to handle clipping in multi-clipping plane cases. By optimizing the hardware and methods around single plane clipping, polygon throughput may be enhanced.
摘要翻译：方法和硬件可以使用专用于单平面限幅的流水线处理单平面剪切操作。可以提供第二管线来处理多裁剪平面情况下的削波。通过优化围绕单平面剪切的硬件和方法，可以增强多边形吞吐量。

5. 发明申请

US20160092239A1 METHOD AND APPARATUS FOR UNSTRUCTURED CONTROL FLOW FOR SIMD EXECUTION ENGINE 有权
标题翻译：用于SIMD执行发动机的非调节控制流的方法和装置
公开(公告)号：US20160092239A1
公开(公告)日：2016-03-31
申请号：US14498505
申请日：2014-09-26
申请人： SUBRAMANIAM MAIYURAN , DARIN M. STARKEY
发明人： SUBRAMANIAM MAIYURAN , DARIN M. STARKEY
IPC分类号： G06F9/38 , G06F9/30 , G06F9/32
CPC分类号： G06F9/3887 , G06F9/30054 , G06F9/30072 , G06F9/321 , G06F9/3851
摘要： An apparatus and method for a SIMD unstructured branching. For example, one embodiment of a processor comprises: an execution unit having a plurality of channels to execute instructions; and a branch unit to process unstructured control flow instructions and to maintain a per channel count value for each channel, the branch unit to store instruction pointer tags for the unstructured control flow instructions in a memory and identify the instruction pointer tags using tag addresses, the branch unit to further enable and disable the channels based at least on the per channel count value.
摘要翻译：一种SIMD非结构化分支的装置和方法。例如，处理器的一个实施例包括：具有执行指令的多个通道的执行单元; 以及分支单元，用于处理非结构化控制流程指令并维持每个通道的每通道计数值，所述分支单元将非结构化控制流程指令的指令指针标记存储在存储器中，并使用标签地址识别指令指针标签，分支单元，以至少基于每个通道计数值进一步启用和禁用通道。

6. 发明申请

US20130305018A1 MFENCE and LFENCE Micro-Architectural Implementation Method and System 有权
标题翻译： MFENCE和LFENCE微建筑实施方法与系统
公开(公告)号：US20130305018A1
公开(公告)日：2013-11-14
申请号：US13942660
申请日：2013-07-15
申请人： SALVADOR PALANCA , STEPHEN FISCHER , SUBRAMANIAM MAIYURAN , SHEKOUFEH QAWAMI
发明人： SALVADOR PALANCA , STEPHEN FISCHER , SUBRAMANIAM MAIYURAN , SHEKOUFEH QAWAMI
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3012 , G06F9/30145 , G06F9/3808 , G06F9/3812 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F2009/45583 , G06F2009/45591
摘要： A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
摘要翻译：一种用于防止内存访问的系统和方法。存储器负载可以围栏，或者所有内存访问都可以被围起来。系统接收一个将内存访问指令分为较早访问和较新访问的防护指令。存储器排序单元内的缓冲器被分配给该指令。比栅栏指令更新的访问指令被停止。旧的访问指令已逐渐退出。当所有较旧的内存访问都已停用时，从缓冲区中分派防护指令。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式