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1. 发明授权

US10297001B2 Reduced power implementation of computer instructions 有权
公开(公告)号：US10297001B2
公开(公告)日：2019-05-21
申请号：US14583300
申请日：2014-12-26
申请人： Subramaniam Maiyuran , Shubh B. Shah , Ashutosh Garg , Jin Xu , Thomas A. Piazza , Jorge F. Garcia Pabon , Michael K. Dwyer
发明人： Subramaniam Maiyuran , Shubh B. Shah , Ashutosh Garg , Jin Xu , Thomas A. Piazza , Jorge F. Garcia Pabon , Michael K. Dwyer
IPC分类号： G06T1/20 , G09G5/00 , G06T15/80 , G09G5/36 , G06F7/00 , G06F9/30
摘要： Systems and methods may provide a graphics processor that may identify operating conditions under which certain floating point instructions may utilize power to fewer hardware resources compared to when the instructions are executing under other operating conditions. The operating conditions may be determined by examining operands used in a given instruction, including the relative magnitudes of the operands and whether the operands may be taken as equal to certain defined values. The floating point instructions may include instructions for an addition operation, a multiplication operation, a compare operation, and/or a fused multiply-add operation.

2. 发明申请

US20180285106A1 HIERARCHICAL GENERAL REGISTER FILE (GRF) FOR EXECUTION BLOCK 审中-公开
公开(公告)号：US20180285106A1
公开(公告)日：2018-10-04
申请号：US15477033
申请日：2017-04-01
申请人： Abhishek R. Appu , Altug Koker , Joydeep Ray , Kamal Sinha , Kiran C. Veernapu , Subramaniam Maiyuran , Prasoonkumar Surti , Guei-Yuan Lueh , David Puffer , Supratim Pal , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
发明人： Abhishek R. Appu , Altug Koker , Joydeep Ray , Kamal Sinha , Kiran C. Veernapu , Subramaniam Maiyuran , Prasoonkumar Surti , Guei-Yuan Lueh , David Puffer , Supratim Pal , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
IPC分类号： G06F9/30 , G06T15/00 , G06T1/60 , G06T1/20 , G06F9/46 , G09G5/36
摘要： In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.

3. 发明授权

US09612835B2 MFENCE and LFENCE micro-architectural implementation method and system 有权
公开(公告)号：US09612835B2
公开(公告)日：2017-04-04
申请号：US13619919
申请日：2012-09-14
申请人： Salvador Palanca , Stephen A. Fischer , Subramaniam Maiyuran , Shekoufeh Qawami
发明人： Salvador Palanca , Stephen A. Fischer , Subramaniam Maiyuran , Shekoufeh Qawami
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40 , G06F9/38
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3012 , G06F9/30145 , G06F9/3808 , G06F9/3812 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F2009/45583 , G06F2009/45591
摘要： A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.

4. 发明申请

US20140320509A1 TECHNIQUES FOR GRAPHICS DATA PREFETCHING 有权
标题翻译：图形数据预处理技术
公开(公告)号：US20140320509A1
公开(公告)日：2014-10-30
申请号：US13870924
申请日：2013-04-25
申请人： WEI-YU CHEN , GUEI-YUAN LUEH , SUBRAMANIAM MAIYURAN
发明人： WEI-YU CHEN , GUEI-YUAN LUEH , SUBRAMANIAM MAIYURAN
IPC分类号： G06T1/20
CPC分类号： G06T1/20
摘要： Various embodiments are generally directed to techniques to prefetch pixel data of one or more pixels adjacent to a pixel for which pixel data is retrieved where the prefetched pixel data may be stored in noncontiguous storage locations. A device comprising a processor component and a hint generation component executed by the processor component to embed a prefetch hint in an executable read instruction, the executable read instruction to retrieve pixel data of a specified pixel and the prefetch hint to retrieve pixel data of an adjacent pixel that is geometrically adjacent to the specified pixel. Other embodiments are described and claimed.
摘要翻译：各种实施例通常涉及用于预取与检索像素数据的像素相邻的一个或多个像素的像素数据的技术，其中预取像素数据可存储在非连续的存储位置中。一种设备，包括由处理器组件执行的处理器组件和提示生成组件，以将预取提示嵌入到可执行读取指令中，该可执行读取指令检索指定像素的像素数据和预取提示以检索邻近的像素数据与指定像素几何相邻的像素。描述和要求保护其他实施例。

5. 发明申请

US20120198208A1 SHARED FUNCTION MULTI-PORTED ROM APPARATUS AND METHOD 有权
标题翻译：共享功能多点ROM设备和方法
公开(公告)号：US20120198208A1
公开(公告)日：2012-08-02
申请号：US13338887
申请日：2011-12-28
申请人： Satish K. Damaraju , Subramaniam Maiyuran
发明人： Satish K. Damaraju , Subramaniam Maiyuran
IPC分类号： G06F9/30
CPC分类号： G06F9/3877 , G06F7/544 , G06F9/3001 , G06F9/30036
摘要： Various embodiments may be disclosed that may share a ROM pull down logic circuit among multiple ports of a processing core. The processing core may include an execution unit (EU) having an array of read only memory (ROM) pull down logic storing math functions. The ROM pull down logic circuit may implement single instruction, multiple data (SIMD) operations. The ROM pull down logic circuit may be operatively coupled with each of the multiple ports in a multi-port function sharing arrangement. Sharing the ROM pull down logic circuit reduces the need to duplicate logic and may result in a savings of chip area as well as a savings of power.
摘要翻译：可以公开可以在处理核心的多个端口中共享ROM下拉逻辑电路的各种实施例。处理核心可以包括具有存储数学函数的只读存储器（ROM）下拉逻辑阵列的执行单元（EU）。 ROM下拉逻辑电路可以实现单指令，多数据（SIMD）操作。 ROM下拉逻辑电路可以在多端口功能共享装置中与多个端口中的每一个可操作地耦合。共享ROM下拉逻辑电路减少了重复逻辑的需要，并且可以节省芯片面积以及节省功率。

6. 发明申请

US20050138341A1 Method and apparatus for a stew-based loop predictor 有权
标题翻译：一种基于炖菜的循环预测器的方法和装置
公开(公告)号：US20050138341A1
公开(公告)日：2005-06-23
申请号：US10739689
申请日：2003-12-17
申请人： Subramaniam Maiyuran , Peter Smith , Stephan Jourdan
发明人： Subramaniam Maiyuran , Peter Smith , Stephan Jourdan
IPC分类号： G06F9/00 , G06F9/32 , G06F9/38
CPC分类号： G06F9/3802 , G06F9/325 , G06F9/3808 , G06F9/3844
摘要： A method and apparatus for a loop predictor for predicting the end of a loop is disclosed. In one embodiment, the loop predictor may have a predict counter to hold a predict count representing the expected number of times that a predictor stew value will repeat during the execution of a given loop. The loop predictor may also have one or more running counters to hold a count of the times that the stew value has repeated during the execution of the present loop. When the counter values match the predictor may issue a prediction that the loop will end.
摘要翻译：公开了一种用于预测环路结束的环路预测器的方法和装置。在一个实施例中，环路预测器可以具有预测计数器，以保持预测计数，该预测计数表示在给定循环的执行期间预测器炖值将重复的预期次数。循环预测器还可以具有一个或多个运行计数器，以在执行当前循环期间保持炖煮值重复的次数的计数。当计数器值匹配时，预测器可以发出循环结束的预测。

7. 发明授权

US06665775B1 Cache dynamically configured for simultaneous accesses by multiple computing engines 有权
标题翻译：缓存动态配置为同时访问多个计算引擎
公开(公告)号：US06665775B1
公开(公告)日：2003-12-16
申请号：US09667688
申请日：2000-09-22
申请人： Subramaniam Maiyuran , Salvador Palanca
发明人： Subramaniam Maiyuran , Salvador Palanca
IPC分类号： G06F1208
CPC分类号： G06F12/0848 , G06F12/084 , G06F12/0846
摘要： A cache has an array with single ported cells and is dynamically accessible simultaneously by multiple computing engines. In a further embodiment, the cache also has a tag array including a first address input, a second address input, and a shared mode input, and a data array electrically coupled to the tag array and including a first address input, a second address input, and a shared mode input.
摘要翻译：缓存具有单个移植单元的阵列，并且可由多个计算引擎同时动态访问。在另一实施例中，高速缓存还具有包括第一地址输入，第二地址输入和共享模式输入的标签阵列，以及电耦合到标签阵列的数据阵列，并且包括第一地址输入，第二地址输入，和共享模式输入。

8. 发明授权

US06604162B1 Snoop stall reduction on a microprocessor external bus 有权
标题翻译：微处理器外部总线上的监听减速
公开(公告)号：US06604162B1
公开(公告)日：2003-08-05
申请号：US09606837
申请日：2000-06-28
申请人： Lokpraveen B. Mosur , Subramaniam Maiyuran
发明人： Lokpraveen B. Mosur , Subramaniam Maiyuran
IPC分类号： G06F1342
CPC分类号： G06F12/0831 , G06F13/4243
摘要： A method and apparatus for reducing snoop stall on an external bus. One method of the present invention comprises retrieving an address and a transaction attribute for a bus transaction during a first of a plurality of request phase packets of the bus transaction. Then it is determined whether the bus transaction is a snoopable memory transaction or not. If the bus transaction is a snoopable memory transaction, a snoop probe is dispatched during the first request phase packet of the transaction. Snooping devices are allowed additional bus clocks to respond to the snoop probe, thereby reducing the number of snoop stalls required to be inserted during the bus transaction.
摘要翻译：一种用于减少外部总线上的窥探失速的方法和装置。本发明的一种方法包括在总线事务的多个请求阶段分组的第一个期间检索总线事务的地址和事务属性。然后确定总线事务是否是可窥探的存储器事务。如果总线事务是可窥探的内存事务，则在事务的第一请求阶段数据包期间调度侦听器探测。侦听设备允许额外的总线时钟响应窥探探针，从而减少在总线事务期间插入所需的监听档位数。

9. 发明授权

US06507219B2 Charge sharing and charge recycling for an on-chip bus 失效
公开(公告)号：US06507219B2
公开(公告)日：2003-01-14
申请号：US09962716
申请日：2001-09-21
申请人： Sanjay Dabral , Ming Zeng , Subramaniam Maiyuran
发明人： Sanjay Dabral , Ming Zeng , Subramaniam Maiyuran
IPC分类号： H03K19094
CPC分类号： G11C7/106 , G06F13/4077 , G11C7/1051 , G11C7/1078 , G11C7/1087 , H03K19/01855 , Y02D10/14 , Y02D10/151
摘要： A method for charge sharing among data conductors of a bus. The bus has a first data conductor and a corresponding data conductor. The method includes detecting the logic levels on the first data conductor and the corresponding data conductor, and generating a charge sharing signal for sharing charge between the first data conductor and the corresponding data conductor.

10. 发明授权

US06356270B2 Efficient utilization of write-combining buffers 失效
标题翻译：高效利用写入组合缓冲区
公开(公告)号：US06356270B2
公开(公告)日：2002-03-12
申请号：US09053231
申请日：1998-03-31
申请人： Vladimir Pentkovski , Hsien-Cheng E. Hsieh , Hsien-Hsin Lee , Subramaniam Maiyuran
发明人： Vladimir Pentkovski , Hsien-Cheng E. Hsieh , Hsien-Hsin Lee , Subramaniam Maiyuran
IPC分类号： G06T160
CPC分类号： G06F9/30043 , G06F9/3824 , G06F12/0875
摘要： The present invention discloses a method and apparatus method for efficient utilization of write-combining buffers for a sequence of non-temporal stores to scattered locations. The method comprises: converting the sequence of non-temporal stores to stores to intermediate buffers; and grouping the stores to intermediate buffers into consecutive non-temporal stores. The consecutive non-temporal stores correspond to adjacent memory locations in the write-combining buffers.
摘要翻译：本发明公开了一种用于对分散位置的非时间存储序列的写合成缓冲器有效利用的方法和装置方法。该方法包括：将非时间存储序列转换为存储到中间缓冲器; 并将商店分组到中间缓冲器到连续的非时间商店。连续的非时间存储对应于写合成缓冲器中的相邻存储器位置。

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