专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

DE3884820T2 未知
公开(公告)号：DE3884820T2
公开(公告)日：1994-01-27
申请号：DE3884820
申请日：1988-07-27
申请人： TOSHIBA KAWASAKI KK , TOSHIBA MICRO CUMPUTER ENG
发明人： MINAGAWA HIDENOBU , TATSUMI YUUICHI , IWAHASHI HIROSHI , ASANO MASAMICHI , NAKAI HIROTO , IMAI MIZUHO
IPC分类号： G11C16/10 , G11C16/24 , G11C16/30 , G11C16/34 , G11C16/06
摘要： A nonvolatile semiconductor memory device comprises a plurality of memory cell circuits each including a nonvolatile memory cell (M11) consisting of a floating gate transistor. The floating gate transistor has its source connected to a reference voltage (VS) via a conductive layer (N1) having a resistance, and a plurality of semiconductor elements are connected in series with the current path of the floating gate transistor between a power source voltage (VP) and the drain of the floating gate transistor. The effective resistances of the conductive layers between the sources of the floating gate transistors and the reference voltage (VS) are different from each other and the resistance values of the corresponding semiconductor elements are selected so as to be inversely proportional to the effective resistances between the sources of the floating gate transistors and the reference voltage (VS).

2. 发明专利

DE3874455T2 未知
公开(公告)号：DE3874455T2
公开(公告)日：1993-04-08
申请号：DE3874455
申请日：1988-07-27
申请人： TOSHIBA KAWASAKI KK , TOSHIBA MICRO CUMPUTER ENG
发明人： MINAGAWA HIDENOBU , TATSUMI YUUICHI , IWAHASHI HIROSHI , ASANO MASAMICHI , NAKAI HIROTO , IMAI MIZUHO
IPC分类号： G11C16/10 , G11C16/24 , G11C16/30 , G11C16/34 , G11C16/06 , G11C11/34
摘要： A nonvolatile semiconductor memory device comprises a plurality of memory cell circuits each including a nonvolatile memory cell (M11) consisting of a floating gate transistor. The floating gate transistor has its source connected to a reference voltage (VS) via a conductive layer (N1) having a resistance, and a plurality of semiconductor elements are connected in series with the current path of the floating gate transistor between a power source voltage (VP) and the drain of the floating gate transistor. The effective resistances of the conductive layers between the sources of the floating gate transistors and the reference voltage (VS) are different from each other and the resistance values of the corresponding semiconductor elements are selected so as to be inversely proportional to the effective resistances between the sources of the floating gate transistors and the reference voltage (VS).

3. 发明专利

DE3884820D1 未知
公开(公告)号：DE3884820D1
公开(公告)日：1993-11-11
申请号：DE3884820
申请日：1988-07-27
申请人： TOSHIBA KAWASAKI KK , TOSHIBA MICRO CUMPUTER ENG
发明人： MINAGAWA HIDENOBU , TATSUMI YUUICHI , IWAHASHI HIROSHI , ASANO MASAMICHI , NAKAI HIROTO , IMAI MIZUHO
IPC分类号： G11C16/10 , G11C16/24 , G11C16/30 , G11C16/34 , G11C16/06
摘要： A nonvolatile semiconductor memory device comprises a plurality of memory cell circuits each including a nonvolatile memory cell (M11) consisting of a floating gate transistor. The floating gate transistor has its source connected to a reference voltage (VS) via a conductive layer (N1) having a resistance, and a plurality of semiconductor elements are connected in series with the current path of the floating gate transistor between a power source voltage (VP) and the drain of the floating gate transistor. The effective resistances of the conductive layers between the sources of the floating gate transistors and the reference voltage (VS) are different from each other and the resistance values of the corresponding semiconductor elements are selected so as to be inversely proportional to the effective resistances between the sources of the floating gate transistors and the reference voltage (VS).

4. 发明专利

DE3874455D1 未知
公开(公告)号：DE3874455D1
公开(公告)日：1992-10-15
申请号：DE3874455
申请日：1988-07-27
申请人： TOSHIBA KAWASAKI KK , TOSHIBA MICRO CUMPUTER ENG
发明人： MINAGAWA HIDENOBU , TATSUMI YUUICHI , IWAHASHI HIROSHI , ASANO MASAMICHI , NAKAI HIROTO , IMAI MIZUHO
IPC分类号： G11C16/10 , G11C16/24 , G11C16/30 , G11C16/34 , G11C16/06 , G11C11/34
摘要： A nonvolatile semiconductor memory device comprises a plurality of memory cell circuits each including a nonvolatile memory cell (M11) consisting of a floating gate transistor. The floating gate transistor has its source connected to a reference voltage (VS) via a conductive layer (N1) having a resistance, and a plurality of semiconductor elements are connected in series with the current path of the floating gate transistor between a power source voltage (VP) and the drain of the floating gate transistor. The effective resistances of the conductive layers between the sources of the floating gate transistors and the reference voltage (VS) are different from each other and the resistance values of the corresponding semiconductor elements are selected so as to be inversely proportional to the effective resistances between the sources of the floating gate transistors and the reference voltage (VS).

5. 发明专利

JPS6318592A NON-VOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS6318592A
公开(公告)日：1988-01-26
申请号：JP15974486
申请日：1986-07-09
申请人： TOSHIBA CORP , TOSBAC COMPUTER SYSTEM CO LTD , TOSHIBA MICRO CUMPUTER ENG
发明人： NAKAI HIROTO , IWAHASHI HIROSHI , ASANO MASAMICHI , SUZUKI KAZUTO , KUMAGAI SHIGERU , SATO ISAO
IPC分类号： H01L21/8247 , G11C17/00 , H01L21/822 , H01L27/04 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PURPOSE:To eliminate a drop in the drain voltage of a memory cell at the time of writing data, to make strong to the unevenness in a process and to write the data at high speed by using a booster circuit as a power switching circuit and applying this voltage to the buffer of a decoder. CONSTITUTION:At the time of an ordinary reading, the same voltage as VCC is impressed to the voltage of a source VPP, signals -W, HD, -HD are respectively logics '1', '0', '1', a transistor T37 is turned on and the output of a node SW1 has the same voltage as the VCC. On the other hand, at the time of writing the data, a higher voltage than the power source VCC is impressed to the power source VPP. The signals -W, HD, -HD go to the logics '0', '1', '0'. Accordingly, a signal from a ring oscillator constituted of inverters I2-I6 is applied to an inverter consisting of transistors T23-T25 and the buffer consisting of transistors T26-T28 through an inverter I7, the potential of the node SW1 is raised for every clock pulse and finally, stable at a voltage higher by the threshold voltage of the transistor T36 than the power source VPP.

6. 发明专利

JPH01130397A NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH01130397A
公开(公告)日：1989-05-23
申请号：JP28768087
申请日：1987-11-14
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG , TOSBAC COMPUTER SYSTEM CO LTD
发明人： NAKAI HIROTO , IWAHASHI HIROSHI , ASANO MASAMICHI , KATO HIDEO , KANAZAWA KAZUHISA , SATO ISAO , KUMAGAI SHIGERU , KIKUCHI SHINICHI , NARITA AKIRA
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE:To improve the stability of operation and to increase a write margin by preventing a leak current from an output line at the time of rise of the potential of the output line. CONSTITUTION:D type transistors T207-T209 are connected in series for the purpose of outputting a boosting voltage to a column decoder 12 and the output line of a data write circuit and the voltage of the output line is fed back. Consequently, the voltage is surely raised at the time of selection and is surely reduced at the time of nonselection. Thus, the power consumption is reduced regardless of the constitution of inexpensive N-channel MOS transistors, and the voltage margin is increased and the write margin is improved.

7. 发明专利

JPH01128459A NON VOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH01128459A
公开(公告)日：1989-05-22
申请号：JP28574887
申请日：1987-11-12
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： IWAHASHI HIROSHI , NAKAI HIROTO , MINAGAWA EISHIN , TATSUMI YUICHI
IPC分类号： G11C17/00 , G11C16/04 , H01L21/822 , H01L21/8246 , H01L21/8247 , H01L27/04 , H01L27/10 , H01L27/112 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PURPOSE:To enable any data to be written in an avalanche region where a higher program efficiency is assured by defining the gradient of a load line upon write operation substantially by resistance. CONSTITUTION:A resistor R is serially inserted between a power supply UP and a load transistor 104, the resistor R is serially inserted between a transistor 104 and a row select transistor C1, and the resistor is serially inserted between a memory cell BL1 and the row select transistor C1. The resistor R is serially inserted between the power supply VP and the drain of the memory cell and set to dominantly define a load line. There is no need of completely defining the load line only by the resistor R. That is, the resistor R may relax the characteristics of a current ID changing in the square with respect to a change 'VG-VIH'' of a MOSFET. Accordingly, for load resistance by the MOSFET and the load resistance R by polysilicon or a diffusion layer, the latter may be set to be larger.

8. 发明专利

JPS6314400A NONVOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS6314400A
公开(公告)日：1988-01-21
申请号：JP15729986
申请日：1986-07-04
申请人： TOSHIBA CORP , TOSBAC COMPUTER SYSTEM CO LTD , TOSHIBA MICRO CUMPUTER ENG
发明人： NAKAI HIROTO , IWAHASHI HIROSHI , ASANO MASAMICHI , SUZUKI KAZUTO , KUMAGAI SHIGERU , SATO ISAO
IPC分类号： G11C29/00 , G11C17/00 , G11C29/12
摘要： PURPOSE:To attain the measurement of an electric characteristic even if the titled memory is sealed into a package by setting all row lines into the non- selecting state before data is read from a memory cell in the erasure state even if all memory cells are erased in advance to apply the similar operation to data read. CONSTITUTION:In setting a voltage V31 at a terminal 31 to a high level to bring all row lines 11 into non-selecting state, and after storage data of the memory cell in the write state substantially are read, an external address signal is fed to the terminal 31 in place of a high voltage. Then one row line corresponding to the address is driven selectively to read the storage data in the memory cell in the erasure state. Thus, data write is executed only once and even with no data erasure, the manufacture cost is made inexpensive and even if the element is sealed in the package, the electric characteristic is measured.

9. 发明专利

JPH0642551B2 失效
公开(公告)号：JPH0642551B2
公开(公告)日：1994-06-01
申请号：JP28574887
申请日：1987-11-12
申请人： TOSHIBA KK , TOSHIBA MICRO CUMPUTER ENG
发明人： IWAHASHI HIROSHI , NAKAI HIROTO , MINAGAWA EISHIN , TATSUMI YUICHI
IPC分类号： G11C17/00 , G11C16/04 , H01L21/822 , H01L21/8246 , H01L21/8247 , H01L27/04 , H01L27/10 , H01L27/112 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792

10. 发明专利

JPH01173399A SEMICONDUCTOR STORAGE 失效
公开(公告)号：JPH01173399A
公开(公告)日：1989-07-10
申请号：JP33052487
申请日：1987-12-26
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： KIKUCHI SHINICHI , IWASAKI HIROSHI , KANAZAWA KAZUHISA , NAKAI HIROTO , KATO HIDEO
IPC分类号： G11C17/00 , G11C7/06 , G11C16/06
摘要： PURPOSE:To suppress the rise of a reference potential and to improve an operating margin to a power source noise by connecting a transistor (TR), which goes to be a load element, between a TR, in which a reading potential and the reference potential are respectively supplied to a gate, and a power source voltage in a sense amplifier. CONSTITUTION:When memory cell storing data are 0, a reading potential Vin goes to be lower than a reference potential Vref and the potential of a node N11 is lowered. Then, the conductive resistance of a TRQ14 rises up. Thus, the potential of a node N12 rises up and the potential Vref is pushed up by the capacity between gates and source and channel of a TRQ12. On the other hand, a TRQ10 connected between TRs Q11 and Q12 and a power source voltage VC is operated as the load element and the potential of a node N13 is decreased. Then, one part of an electric charge to push up the potential Vref is divided to the TRs Q11 and Q12 and the rise of the potential Vref is controlled. Difference between the potential Vin and the Vref is kept to a prescribed potential and the operating margin is improved to the power source noise. Then, reliability is improved.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式