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1. 发明专利

JP2006294795A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006294795A
公开(公告)日：2006-10-26
申请号：JP2005112142
申请日：2005-04-08
申请人： Toshiba Corp , 株式会社東芝
发明人： OKANE NOBORU , MATSUSHIMA RYOJI , YAMAMORI KAZUHIRO , SAGARA JUNYA , IIZUKA YOSHIO , ONISHI KUNIYUKI
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07
CPC分类号： H01L23/49575 , H01L24/48 , H01L24/49 , H01L24/92 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48095 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/48475 , H01L2224/49113 , H01L2224/73265 , H01L2224/85051 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/181 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of incorporating as many bare chips as possible without raising defective fractions such as a short circuit, and without enlarging the outside dimension of a package, and to provide its manufacturing method.
SOLUTION: The semiconductor device of this embodiment arranges two bare chips 3 and 4 on both sides of a silicon spacer 2 put between on the upper surface of a bed frame 1 (supporting substrate), and arranges two bare chips 3 and 4 on both sides of the silicon spacer 2 put between also on the undersurface of the bed frame 1. On both sides in a horizontal direction sandwiching the bed frame 1, an inner lead 5 is arranged in such a way that the inner lead 5 and a pad of the bare chips 3 and 4 are connected with bonding wires 6 and 7. The height of the bonding wire 7 is restricted so that the bonding wire 7 for connecting a pad of the bare chip 3 of one end side of a silicon spacer 2 to the inner lead 5 may not be contacted with the bare chip 3 of the other end side of the same silicon spacer 2.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其能够并入尽可能多的裸芯片，而不会引起诸如短路的缺陷部分，并且不扩大封装的外部尺寸，并提供其制造方法。解决方案：本实施例的半导体器件将两个裸芯片3和4布置在放置在床架1（支撑基板）的上表面之间的硅间隔物2的两侧，并且布置两个裸芯片3和4 在硅衬垫2的两侧也放置在床架1的下表面之间。在夹着床架1的水平方向的两侧，内引线5被布置成使得内引线5和裸芯片3和4的焊盘与接合线6和7连接。接合线7的高度被限制，使得用于连接硅间隔件2的一端侧的裸芯片3的焊盘的接合线7 内引线5可能不与同一硅隔离物2的另一端侧的裸芯片3接触。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JPS6279639A WIRE BONDING DEVICE 失效
公开(公告)号：JPS6279639A
公开(公告)日：1987-04-13
申请号：JP21803185
申请日：1985-10-02
申请人： TOSHIBA CORP
发明人： YAMAMORI KAZUHIRO
IPC分类号： H01L21/60
摘要： PURPOSE:To provide a press plate with elasticity preventing the thermal pressure fixing strength from declining by a method wherein a stay and a stay retainer are connected by spring bodies while a pin to be actuated corresponding to the actions of a lifting mechanism is arranged in a cavity provided in the stay retainer. CONSTITUTION:A press plate retaining mechanism 4 is composed of a stay retainer 5, a press plate 6 and springs 8 provided between the two components 5 and 6. A connecting cavity 7 is formed in a retainer retaining the legs provided on four corners of the press plate retainer 5 and the legs; a pin 7 able to abut against a retaining bar 3 is arranged in the cavity 7; and a part of this pin 7 is insertedly positioned in the springs 8. The press plate 6 is provided with elastic protrusions 9 to press down a bed part and a lead part of lead frame carried to a carrier surface 40. In such a constitution, the stay 6 is lifted by the pin 7 which is actuated by the third lifting mechanism before the lead frame is carried; the press plate 6 is lowered as soon as the lead frame is carried; and the lead frame is pressure-held between the lifted heater blocks to assure the thermal pressure fixing.

3. 发明专利

JP2008187109A STACKED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：JP2008187109A
公开(公告)日：2008-08-14
申请号：JP2007021060
申请日：2007-01-31
申请人： TOSHIBA CORP
发明人： YAMAMORI KAZUHIRO , ISHIDA KATSUHIRO
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
摘要： PROBLEM TO BE SOLVED: To reduce, when a plurality of semiconductor elements are stacked, a gap between the semiconductor elements while reducing loop heights of metallic wires connected to the semiconductor element of a lower stage to prevent the occurrence of faulty insulation, a short circuit or the like which are caused by contact with the semiconductor element of an upper stage. SOLUTION: A stacked semiconductor device 1 includes a first semiconductor element 5 mounted to a circuit substrate 2, and a second semiconductor element 11 stacked on the first semiconductor element 5 via a spacer layer 12. Electrode pads 7 of the first semiconductor element 5 are electrically connected to joints 4 of the circuit substrate 2 via first metallic wires 9. Portions near the joints of the first metallic wires 9 with the electrode pads 7 are in contact with an insulating protective film 8 covering the surface of the first semiconductor element 5. COPYRIGHT: (C)2008,JPO&INPIT

4. 发明专利

JP2007035864A Semiconductor package 审中-公开
标题翻译：半导体封装
公开(公告)号：JP2007035864A
公开(公告)日：2007-02-08
申请号：JP2005216167
申请日：2005-07-26
申请人： Toshiba Corp , 株式会社東芝
发明人： OKANE NOBORU , MATSUSHIMA RYOJI , YAMAMORI KAZUHIRO , SAGARA JUNYA , IIZUKA YOSHIO , ONISHI KUNIYUKI
IPC分类号： H01L23/12
CPC分类号： H01L25/0657 , H01L23/49816 , H01L24/48 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06555 , H01L2225/06572 , H01L2225/06575 , H01L2924/00014 , H01L2924/09701 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To further thin a semiconductor package to which a BGA structure has been applied, and to further achieve high-density packaging or the like in a semiconductor element. SOLUTION: The semiconductor package 1 has a circuit board 3 having the wiring network of electrodes 6, 9 formed on both front and rear surfaces as a package substrate. A metal bump 2 connected to the electrodes 6, 9 on both the front and rear surfaces via the wiring network is formed as an external connection terminal on the back of the circuit board 3. One or a plurality of semiconductor elements 11, 12 electrically connected to the electrode 6 at the front side are mounted on a first element mount section 5 provided at the front side of the circuit board 3. One or a plurality of semiconductor elements 19, 23 electrically connected to the electrode 9 at the rear side are mounted on a second element mount section 8 formed at the rear side of the circuit board 3. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了进一步薄化已经应用了BGA结构的半导体封装，并且进一步实现半导体元件中的高密度封装等。解决方案：半导体封装1具有电路板3，电路板3具有形成在前表面和后表面上的电极6,9的布线网络作为封装基板。在电路板3的背面形成有通过布线网络连接到前后表面上的电极6,9的金属凸块2，一个或多个半导体元件11,12电连接在前侧的电极6安装在设置在电路基板3的前侧的第一元件安装部分5上。电连接到后侧的电极9的一个或多个半导体元件19,23被安装在形成在电路板3的后侧的第二元件安装部分8上。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JPH09283551A BONDING AND BONDING DEVICE 失效
公开(公告)号：JPH09283551A
公开(公告)日：1997-10-31
申请号：JP9534496
申请日：1996-04-17
申请人： TOSHIBA CORP
发明人： YAMAMORI KAZUHIRO
IPC分类号： H01L21/60
摘要： PROBLEM TO BE SOLVED: To ensure the bonding strength of a fine metal wire and the reliability of bonding of the wire by a method wherein the point on one side of the fine metal wire is pressure bonded to an electrode pad, the fine metal wire of a length necessary for connecting the electrode pad with a lead is pulled out, the end part of the fine metal wire is heated to recrystallize, and the recrystallized end part is connected with the lead. SOLUTION: A fine metal wire 1 is made to pass through a pressure bonding tool 17 and a ball 5 formed on the point of the wire 1 is pressure bonded to an electrode pad 3 on a semiconductor element 2 using the tool 17. After this, with the time when the tool 11 feeds out the wire 1, the tool 11 is made to rise to pull out the wire 1 to a length P necessary for connecting the pad 2 with a lead 4 and a capillary 21 on the point of the tool 11 is heated by a heating device 6 to recrystallize. Moreover, the recrystallized capillary 21 on the point of the tool 17 is made to reach a position R on the lead 4 to make the wire 1 pressure bond to the lead 4. Thereby, the bonding strength of the wire 1 can be ensured.

6. 发明专利

JPH05160192A SEMICONDUCTOR FABRICATING SYSTEM 失效
公开(公告)号：JPH05160192A
公开(公告)日：1993-06-25
申请号：JP32262691
申请日：1991-12-06
申请人： TOSHIBA CORP
发明人： NAGAOKA TETSUYA , YAMAMORI KAZUHIRO
IPC分类号： H01L21/00 , H01L21/60
摘要： PURPOSE:To facilitate correction of wire cut position when semiconductor chips are wire bonded each other. CONSTITUTION:The inventive semiconductor fabricating system comprises a pattern recognition mechanism for automatically recognizing pads to be bonded on semiconductor chips 2 and 4, and a bonder control section for automatically setting the coordinates of a wire cut point C1 at the time of forming a metal ball 6-1 and the coordinates of a wire cut point C2 after connection of a wire 7 onto the metal ball 6-1 based on information fed from the pattern recognizing mechanism and the diameter of the wire 7. According to the constitution, the wire cut points C1, C2 are corrected automatically when bond points B1, B2 are corrected through the pattern recognizing mechanism.

7. 发明专利

JPS61172343A WIRE BONDING PROCESS AND APPARATUS THEREOF 失效
公开(公告)号：JPS61172343A
公开(公告)日：1986-08-04
申请号：JP1250385
申请日：1985-01-28
申请人： TOSHIBA CORP
发明人： YAMAMORI KAZUHIRO
IPC分类号： H01L21/603 , H01L21/60
摘要： PURPOSE:To make bonding process highly reliable by a method wherein, after forming a ball utilizing a copper or copper alloy made bonding wire, reducing high temperature gas is jetted to the part near the end of a capacity until the time immediately before forming the next ball. CONSTITUTION:When a capillary 1 is on the uppermost position, while jetting inert gas from an inert gas nozzle 12 to a bonding wire 3, an electric torch 8 discharges power toward the bonding wire 3 to form a ball means of melting the end of bonding wire 3. After forming a ball, reducing high temperature gas is jetted from a reducing high temperature gas nozzle 13 to the ball and the bonding wire 3 to pressure weld the end of capillary 1 into specified lead parts of a semiconductor chip 5 and a leadframe 6. Successively after cutting off the bonding wire 3, the capillary 1 may be reset to the uppermost position, but the reducing high temperature gas is jetted until the time immediately before the capillary 1 is reset to said position to prevent the end of bonding wire 3 from being oxidized without the possibility of causing defective bonding and broken chip making it feasible to bond copper or copper alloy made bonding wire.

8. 发明专利

JPH08130232A SEMICONDUCTOR MANUFACTURING EQUIPMENT 失效
公开(公告)号：JPH08130232A
公开(公告)日：1996-05-21
申请号：JP26777694
申请日：1994-10-31
申请人： TOSHIBA CORP
发明人： YAMAMORI KAZUHIRO , HORI MASAHIKO
IPC分类号： H01L21/603 , H01L21/60
摘要： PURPOSE: To provide a semiconductor manufacturing equipment having mechanism which automatically controls dynamic load characteristics applied to a bonding part at the time of wire bonding. CONSTITUTION: A semiconductor manufacturing equipment is provided with a tool holder 13 having a sensor 12 in the vicinity of the center. The sensor 12 electrically converts the deflection (reactive force) of the tool holder 13 and transmits it as a signal to a control part 20 via an amplifier 19. A dynamic load waveform obtained by the above method is compared with a load waveform which is previously set, and the difference is applied to a linear motor coil.

9. 发明专利

JPH06132344A WIRE BONDING DEVICE 失效
公开(公告)号：JPH06132344A
公开(公告)日：1994-05-13
申请号：JP28300292
申请日：1992-10-21
申请人： TOSHIBA CORP
发明人： YAMAMORI KAZUHIRO
IPC分类号： H01L21/60
摘要： PURPOSE:To obtain an optimum loop shape and a tail quantity in a stable manner by simply and independently controlling the clamper part of a wire bonding device. CONSTITUTION:A tool part A has a tool-driving motor 21, and a tool 24 is driven by this driving motor 21. On the other hand, a clamper B has a clamper- driving motor 25, and a clamper 28 is driven by this driving motor 25 independent of the driving of the tool. Also, on the clamper part B, a voice coil 27, on which the load force which holds the metal fine wire of the clamper 28, is provided.

10. 发明专利

JPH05343446A 失效
公开(公告)号：JPH05343446A
公开(公告)日：1993-12-24
申请号：JP15225692
申请日：1992-06-11
申请人： TOSHIBA CORP
发明人： YAMAMORI KAZUHIRO
IPC分类号： H01L21/52 , H01L23/50
摘要： PURPOSE:To provide a method for die bonding in which wettability of solder is improved and a semiconductor chip can be satisfactorily adhered to an island. CONSTITUTION:In order to remove an oxide film on an island 15, reducing inert gas B is sprayed to the island 15 by a heating nozzle 16. Immediately thereafter, a solder pellet 21 is placed on the island 15. Then, in order to remelt the pellet 21 and to completely remove the film, the gas B is blown to the pellet 21 on the island 15 by the nozzle 16. Immediately thereafter, a semiconductor chip 23 is adhered to the island 15 through the pellet 21.

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