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1. 发明专利

JP2008108971A Wire bonding apparatus and method 有权
标题翻译：电线连接装置和方法
公开(公告)号：JP2008108971A
公开(公告)日：2008-05-08
申请号：JP2006291574
申请日：2006-10-26
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAO MITSUHIRO , ISHIDA KATSUHIRO , OKANE NOBORU , SAGARA JUNYA
IPC分类号： H01L21/60
CPC分类号： B23K20/005 , H01L24/78 , H01L24/85 , H01L2224/78301 , H01L2224/786 , H01L2224/851 , H01L2224/85148 , H01L2224/85205 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01025 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2224/48 , H01L2224/45099 , H01L2224/05599 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a wire bonding apparatus capable of suppressing the wire deformation accompanying a tail cutting operation. SOLUTION: The wire bonding apparatus has a capillary 2 for inserting a wire 1 thereinto, a clamper 3 capable of supporting the wire 1 in a sandwiching way, and a load sensor 6 for measuring the load applied to the wire 1. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够抑制伴随尾切割操作的线变形的引线接合装置。引线接合装置具有用于将导线1插入其中的毛细管2，能够以夹持方式支撑线1的夹持器3和用于测量施加到线1的负载的负载传感器6。 P>版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2011071216A Semiconductor device and adhesive sheet 有权
标题翻译：半导体器件和粘合片
公开(公告)号：JP2011071216A
公开(公告)日：2011-04-07
申请号：JP2009219339
申请日：2009-09-24
申请人： Toshiba Corp , 株式会社東芝
发明人： HAYASHI HIDEKAZU , TOMITA HIROSHI , SAGARA JUNYA , TAKU SHINYA , KUROSAWA TETSUYA , KOGASAKI NORIHIRO , KITAJIMA YUKIKO
IPC分类号： H01L25/065 , C09J7/00 , C09J11/00 , C09J201/00 , H01L21/52 , H01L25/07 , H01L25/18
CPC分类号： C09J163/00 , C08K3/08 , C08K5/0091 , C08L63/00 , H01L23/3121 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/29 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/484 , H01L2224/732 , H01L2224/73265 , H01L2225/0651 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/0102 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01051 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/01088 , H01L2924/0665 , H01L2924/181 , H01L2924/1815 , H01L2924/00 , H01L2924/00012 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/45099 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that prevents the deterioration of characteristics of the semiconductor device, caused by diffusing a metal impurity ion into a semiconductor device region; and to provide an adhesive sheet. SOLUTION: The semiconductor device 1 includes: a substrate 3; a first semiconductor chip that is provided on the substrate 3; a second semiconductor chip that is provided on the first semiconductor chip and whose back surface is processed to be a mirror surface; and the adhesive sheet 5 that is provided between the first and second semiconductor chips and includes a metal impurity ion-trapping agent for trapping metal impurity ion. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其防止由于将金属杂质离子扩散到半导体器件区域而导致的半导体器件的特性劣化; 并提供粘合片。解决方案：半导体器件1包括：衬底3; 设置在基板3上的第一半导体芯片; 第二半导体芯片，设置在第一半导体芯片上，其后表面被加工成镜面; 以及设置在第一和第二半导体芯片之间并且包括用于捕获金属杂质离子的金属杂质离子捕获剂的粘合片5。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2003031616A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2003031616A
公开(公告)日：2003-01-31
申请号：JP2001215159
申请日：2001-07-16
申请人： Toshiba Corp , 株式会社東芝
发明人： SAGARA JUNYA
IPC分类号： H01L23/29 , H01L21/60 , H01L23/31
CPC分类号： H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the same in which an adverse effect on the environment is rather small, a bump can be formed easily, productivity is excellent and reliability of connection is high. SOLUTION: In this semiconductor device, a chip bump 4 and a substrate bump 5 are provided respectively on a semiconductor chip 2 and a substrate 3, the bumps 4, 5 are connected with each other, and the semiconductor chip 2 and substrate 3 are individually sealed with synthetic resin 7 for sealing. One chip bump 4 is formed by non-electrolytic nickel plating in the size smaller than the substrate bump 5, while the other substrate bump 5 is formed by tin plating or tin-silver plating. The chip bump 4 is connected to the substrate bump 5 in the manner that a diffused layer 6 is partly embedded through metal coupling formed to the boundary area.
摘要翻译：要解决的问题：为了提供对环境的不利影响相当小的半导体器件及其制造方法，可以容易地形成凸起，生产率优异并且连接的可靠性高。解决方案：在该半导体器件中，分别在半导体芯片2和基板3上设置芯片凸块4和基板凸块5，凸块4,5彼此连接，并且半导体芯片2和基板3分别用合成树脂7密封用于密封。一个芯片凸块4通过非电解镀镍形成，其尺寸小于衬底凸块5，而另一个衬底凸块5通过镀锡或镀锡镀层形成。芯片凸块4以通过形成在边界区域上的金属耦合部分地嵌入扩散层6的方式连接到基板凸块5。

4. 发明专利

JP2010219567A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2010219567A
公开(公告)日：2010-09-30
申请号：JP2010154071
申请日：2010-07-06
申请人： Toshiba Corp , 株式会社東芝
发明人： OKANE NOBORU , MATSUSHIMA RYOJI , YAMAMORI KAZUHIRO , SAGARA JUNYA , IIZUKA YOSHIO , ONISHI KUNIYUKI
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/48465 , H01L2224/73265 , H01L2224/92247 , H01L2924/01014 , H01L2924/3025 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device incorporating as many bare chips as possible without increasing the contour dimension of a package nor increasing percent defective such as short-circuiting.
SOLUTION: In this semiconductor device, two bare chips 3, 4 are arranged on the upper surface of a bed frame 1 (support substrate) by interposing a silicon spacer 2 therebetween, and two bare chips 3, 4 are arranged also on the undersurface of the bed frame 1 by interposing a silicon spacer 2 therebetween. Inner leads 5 are arranged on both horizontal sides by interposing the bed frame 1 therebetween, and the inner leads 5 are connected to the pads of the bare chips 3, 4 through bonding wires 6, 7. The height of the bonding wire 7 is limited to prevent the bonding wire 7 for connecting the pad of the bare chip 3 on one end side of the silicon spacer 2 to the inner lead 5 from contacting the bare chip 3 on the other end side of the same silicon spacer 2.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种在不增加封装的轮廓尺寸的情况下并入尽可能多的裸芯片的半导体器件，也不增加诸如短路之类的缺陷。解决方案：在该半导体器件中，通过在其间插入硅隔离物2而在床架1（支撑基板）的上表面上设置两个裸芯片3,4，并且还将两个裸芯片3,4也布置在床架1的下表面之间插入硅隔离物2。内引线5通过将床架1插入其间而布置在两个水平侧上，并且内引线5通过接合线6,7连接到裸芯片3,4的焊盘。接合线7的高度受到限制以防止用于将硅衬垫2的一端侧的裸芯片3的焊盘与内引线5连接的接合线7不与同一硅衬垫2的另一端侧的裸芯片3接触。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2009094432A Method for manufacturing stacked semiconductor package 审中-公开
标题翻译：用于制造堆叠半导体封装的方法
公开(公告)号：JP2009094432A
公开(公告)日：2009-04-30
申请号：JP2007266307
申请日：2007-10-12
申请人： Toshiba Corp , 株式会社東芝
发明人： SAGARA JUNYA , TAKU SHINYA , KUROSAWA TETSUYA
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/0657 , H01L21/6835 , H01L24/24 , H01L24/82 , H01L2221/6834 , H01L2224/24051 , H01L2224/24145 , H01L2224/24226 , H01L2224/24998 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/76155 , H01L2224/82001 , H01L2224/82007 , H01L2224/82102 , H01L2225/06524 , H01L2225/06562 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/10157 , H01L2924/10253 , H01L2924/19041 , H01L2924/30105 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a stacked semiconductor package composed by stacking a plurality of semiconductor chips with electrodes, for which insulating layers are formed at the sides of the plurality of semiconductor chips and the plurality of semiconductor chips are electrically connected through the insulating layers, easily and inexpensively.
SOLUTION: The method for manufacturing the stacked semiconductor package where the plurality of semiconductor chips with the electrodes are stacked includes: a process of forming the insulating layers at portions of a wafer corresponding to sides of the plurality of semiconductor chips when obtaining the plurality of semiconductor chips by working the wafer; and a process of forming wiring over the insulating layers at the portions equivalent to the sides of the plurality of semiconductor chips and electrically connecting the plurality of semiconductor chips through the electrodes.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：为了提供一种堆叠的半导体封装，其通过将多个半导体芯片与电极堆叠而形成，在多个半导体芯片的侧面形成有绝缘层，并且多个半导体芯片通过绝缘层，容易和廉价。解决方案：堆叠半导体封装的制造方法，其中具有电极的多个半导体芯片堆叠包括：在获得第一半导体芯片时，在与半导体芯片的侧面相对应的晶片的部分处形成绝缘层的工艺多个半导体芯片通过加工晶片; 以及在与所述多个半导体芯片的侧面等效的部分上在所述绝缘层上形成布线的工序，并且通过所述电极电连接所述多个半导体芯片。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2007035865A Semiconductor package and manufacturing method thereof 审中-公开
标题翻译：半导体封装及其制造方法
公开(公告)号：JP2007035865A
公开(公告)日：2007-02-08
申请号：JP2005216168
申请日：2005-07-26
申请人： Toshiba Corp , 株式会社東芝
发明人： OKANE NOBORU , MATSUSHIMA RYOJI , YAMAMORI KAZUHIRO , SAGARA JUNYA , IIZUKA YOSHIO , ONISHI KUNIYUKI , YOSHIMURA ATSUSHI
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L23/49575 , H01L24/32 , H01L24/48 , H01L24/83 , H01L2224/2919 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/83191 , H01L2224/8385 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/0665 , H01L2924/07802 , H01L2924/181 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To thin a semiconductor element and further a package itself by suppressing the occurrence of a failure caused by bonding to an upper-stage side semiconductor element in a stack-type semiconductor package using a lead frame. SOLUTION: The semiconductor package 1 has the lead frame 2 having an element mount section 3 and a lead section 4. A first semiconductor element 5 and a second semiconductor element 9 are successively laminated and mounted at least on the first main surface 3a of the element mount section 3. An insulating resin layer functioning as a second adhesive layer 10 is filled between the first semiconductor element 5 and the second semiconductor element 9. The element connection side edge of a first bonding wire 8 connected to the first semiconductor element 5 is buried into the insulating resin layer 10. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：通过抑制使用引线框在堆叠型半导体封装中与上级侧半导体元件的接合引起的故障的发生，来使半导体元件和封装本身变薄。解决方案：半导体封装1具有引线框架2，其具有元件安装部分3和引线部分4.第一半导体元件5和第二半导体元件9依次层叠并安装在第一主表面3a上用作第二粘合层10的绝缘树脂层填充在第一半导体元件5和第二半导体元件9之间。连接到第一半导体元件的第一接合线8的元件连接侧边缘 5被埋入绝缘树脂层10中。（C）2007，JPO＆INPIT

7. 发明专利

JP2011181951A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2011181951A
公开(公告)日：2011-09-15
申请号：JP2011103130
申请日：2011-05-02
申请人： Toshiba Corp , 株式会社東芝
发明人： KUROSAWA TETSUYA , SAGARA JUNYA , TAKU SHINYA , KIRITANI MIYOSHI , SHIMIZU NORIKO
IPC分类号： H01L21/301 , H01L21/67 , H01L21/683
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, which is capable of manufacturing a high-quality semiconductor device at a low cost while suppressing problems incident to poor dicing and thinning of a semiconductor chip. SOLUTION: Trenches 120 are formed along dicing lines on an element forming surface side of a semiconductor wafer 100 where the formation of elements has finished, and an adhesive tape 24 is stuck to the element formation surface. The semiconductor wafer is made thin by removing the backside of the semiconductor wafer and diced at the same time, and the backside of the diced semiconductor wafer is coated with an adhesive 150. Subsequently, the adhesive tape 24 is stripped by being sucked on a holding table 3 having a wafer sucking portion formed of a porous material and separated into a plurality of suction areas. The suction area and a suction passage are switched as the stripping progresses. After stripping the adhesive tape is completed, each individual semiconductor chip 1 is picked up by a suction collet. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，其能够以低成本制造高品质的半导体器件，同时抑制半导体芯片的切割不良和薄片化的问题。解决方案：在形成元件的半导体晶片100的元件形成表面侧上的切割线形成沟槽120，并且粘合带24粘附到元件形成表面。通过去除半导体晶片的背面并同时切割半导体晶片，使切割的半导体晶片的背面涂覆有粘合剂150，从而使粘合带24被吸附在保持台3具有由多孔材料形成并分离成多个抽吸区域的晶片吸取部分。抽吸区域和抽吸通道随着剥离进行而被切换。剥离胶带后，每个单独的半导体芯片1被抽吸夹头拾取。版权所有（C）2011，JPO＆INPIT

8. 发明专利

JP2010283204A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2010283204A
公开(公告)日：2010-12-16
申请号：JP2009136186
申请日：2009-06-05
申请人： Toshiba Corp , 株式会社東芝
发明人： KUROSAWA TETSUYA , SAGARA JUNYA , TAKU SHINYA , TOGASAKI NORIHIRO
IPC分类号： H01L21/301 , H01L23/12 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L21/78 , H01L21/561 , H01L21/6835 , H01L21/6836 , H01L23/3185 , H01L23/562 , H01L24/24 , H01L24/27 , H01L24/29 , H01L24/82 , H01L24/83 , H01L25/0657 , H01L2224/24051 , H01L2224/24145 , H01L2224/24225 , H01L2224/24226 , H01L2224/24998 , H01L2224/2919 , H01L2224/32145 , H01L2224/76155 , H01L2224/82001 , H01L2224/82007 , H01L2224/82102 , H01L2224/83101 , H01L2224/83191 , H01L2224/838 , H01L2224/92 , H01L2225/06524 , H01L2225/06551 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0665 , H01L2924/30105 , H01L2924/00 , H01L2924/3512
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device that prevents occurrence of a defect due to insufficient adhesion between a protective film and a semiconductor substrate. SOLUTION: The method of manufacturing the semiconductor device includes the steps of: forming a plurality of first grooves on a first principal surface of the semiconductor substrate having first and second principal surfaces; forming insulating members having upper surfaces positioned above the first principal surface in the first grooves; partially removing parts of the insulating members above the first principal surface; forming second grooves in the insulating members after the removal; and sticking the protective film on the first principal surface. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，该半导体器件防止由于保护膜和半导体衬底之间的不充分粘附而导致的缺陷的发生。解决方案：制造半导体器件的方法包括以下步骤：在具有第一和第二主表面的半导体衬底的第一主表面上形成多个第一沟槽; 形成绝缘构件，其具有位于所述第一凹槽中的所述第一主表面上方的上表面; 在第一主表面上部分去除部分绝缘构件; 在去除之后在绝缘构件中形成第二凹槽; 并将保护膜粘贴在第一主表面上。版权所有（C）2011，JPO＆INPIT

9. 发明专利

JP2007035864A Semiconductor package 审中-公开
标题翻译：半导体封装
公开(公告)号：JP2007035864A
公开(公告)日：2007-02-08
申请号：JP2005216167
申请日：2005-07-26
申请人： Toshiba Corp , 株式会社東芝
发明人： OKANE NOBORU , MATSUSHIMA RYOJI , YAMAMORI KAZUHIRO , SAGARA JUNYA , IIZUKA YOSHIO , ONISHI KUNIYUKI
IPC分类号： H01L23/12
CPC分类号： H01L25/0657 , H01L23/49816 , H01L24/48 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06555 , H01L2225/06572 , H01L2225/06575 , H01L2924/00014 , H01L2924/09701 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To further thin a semiconductor package to which a BGA structure has been applied, and to further achieve high-density packaging or the like in a semiconductor element. SOLUTION: The semiconductor package 1 has a circuit board 3 having the wiring network of electrodes 6, 9 formed on both front and rear surfaces as a package substrate. A metal bump 2 connected to the electrodes 6, 9 on both the front and rear surfaces via the wiring network is formed as an external connection terminal on the back of the circuit board 3. One or a plurality of semiconductor elements 11, 12 electrically connected to the electrode 6 at the front side are mounted on a first element mount section 5 provided at the front side of the circuit board 3. One or a plurality of semiconductor elements 19, 23 electrically connected to the electrode 9 at the rear side are mounted on a second element mount section 8 formed at the rear side of the circuit board 3. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了进一步薄化已经应用了BGA结构的半导体封装，并且进一步实现半导体元件中的高密度封装等。解决方案：半导体封装1具有电路板3，电路板3具有形成在前表面和后表面上的电极6,9的布线网络作为封装基板。在电路板3的背面形成有通过布线网络连接到前后表面上的电极6,9的金属凸块2，一个或多个半导体元件11,12电连接在前侧的电极6安装在设置在电路基板3的前侧的第一元件安装部分5上。电连接到后侧的电极9的一个或多个半导体元件19,23被安装在形成在电路板3的后侧的第二元件安装部分8上。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2006216692A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006216692A
公开(公告)日：2006-08-17
申请号：JP2005026699
申请日：2005-02-02
申请人： Toshiba Corp , 株式会社東芝
发明人： KUROSAWA TETSUYA , SAGARA JUNYA
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07
CPC分类号： H01L24/27 , H01L24/73 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73204 , H01L2224/73265 , H01L2224/78301 , H01L2224/85181 , H01L2224/92247 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/07802 , H01L2924/10156 , H01L2924/10158 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/3512 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To make a package thin without causing failure. SOLUTION: A plurality of chips 12-1 to 12-3 are stacked on a substrate 11 having external connection electrodes 14-1, 14-2, 14-3 and packaged while being wire bonded. At least one chip stacked on a chip is provided, at positions corresponding to bonding pads 15-2, 15-3 on the rear surface, with overhang portions 17-2, 17-3 having a starting point on the inside of the bonding pad and becoming thinner toward the outer circumference up to the end point reaching the sidewall and forming an air gap for containing the ball bonding portion between the overhang portion and the major surface of a chip 12-1 arranged at a lower stage, and insulation layers 18-2, 18-3 formed to cover the overhang portions and preventing contact of the bonding wire of the chip arranged at a lower stage and a chip arranged at an upper stage. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：使包装薄而不会导致故障。解决方案：多个芯片12-1至12-3堆叠在具有外部连接电极14-1,14-2,14-3的基板11上，并且在被引线接合时封装。在与芯片背面的接合焊盘15-2,15-3相对应的位置上设有堆叠在芯片上的至少一个芯片，其中伸出部分17-2,17-3在焊盘的内侧具有起点并且朝向外圆周变薄，直到到达侧壁的端点，并且形成用于容纳在布置在下层的芯片12-1的伸出部分和主表面之间的球接合部分的气隙，并且绝缘层18 -2,18-3形成为覆盖突出部分并防止布置在下层的芯片的接合线和布置在上层的芯片的接触。版权所有（C）2006，JPO＆NCIPI

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