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    • 1. 发明专利
    • Semiconductor device
    • 半导体器件
    • JP2014064028A
    • 2014-04-10
    • JP2013250090
    • 2013-12-03
    • Toshiba Corp株式会社東芝
    • NOZU TETSUO
    • H01L21/822H01L21/8234H01L27/04H01L27/06H01L27/088
    • PROBLEM TO BE SOLVED: To provide a semiconductor device that has large ESD resistance and includes an ESD protection diode with a reduced ineffective area.SOLUTION: A semiconductor device includes: a semiconductor substrate having a first region including a first semiconductor element and a second region surrounding the first region; an insulating film provided on the semiconductor substrate; and a second semiconductor element provided on the second region via a part of the insulating film. The second semiconductor element has: a semiconductor layer having long sides along the outer periphery of the semiconductor substrate and short sides crossing the long sides; a first electrode extending along the long sides on the semiconductor layer; a second electrode arranged side by side with the first electrode; and a PN junction extending between the first electrode and the second electrode. The distance between each of the first electrode and the second electrode and the short sides is larger than the distance between the PN junction and the short sides.
    • 要解决的问题:提供一种具有大的ESD电阻的半导体器件,并且包括具有降低的无效面积的ESD保护二极管。解决方案:半导体器件包括:半导体衬底,具有包括第一半导体元件和第二区域的第一区域 围绕第一区域; 设置在半导体基板上的绝缘膜; 以及经由所述绝缘膜的一部分设置在所述第二区域上的第二半导体元件。 第二半导体元件具有:具有沿半导体基板的外周长边的半导体层和与长边交叉的短边; 沿半导体层的长边延伸的第一电极; 与第一电极并排布置的第二电极; 以及在第一电极和第二电极之间延伸的PN结。 第一电极和第二电极和短边之间的距离大于PN结与短边之间的距离。
    • 2. 发明专利
    • Bi-directional constant voltage diode
    • 双向恒压二极管
    • JP2012064706A
    • 2012-03-29
    • JP2010206869
    • 2010-09-15
    • Toshiba Corp株式会社東芝
    • NOZU TETSUO
    • H01L29/866
    • H01L29/861H01L29/6609H01L29/66098H01L29/732
    • PROBLEM TO BE SOLVED: To provide a bi-directional constant voltage diode having high breakdown voltage.SOLUTION: An N-type first semiconductor layer 12 is formed on an inner surface of a first recess part 11c of an N-type semiconductor substrate 11 so as to generate a second recess part 51a being smaller than the first recess part; and has a lower first impurity concentration than that of the semiconductor substrate 11. A P-type second semiconductor layer 13 is formed on an inner surface of the second recess part 51a so as to generate a third recess part 52a being smaller than the second recess part 51a; and has a second impurity concentration. An P-type third semiconductor layer 14 is formed on an inner surface of the third recess part 52a so as to generate a fourth recess part 53a being smaller than the third recess part 52a; and has a third impurity concentration higher than the second impurity concentration. A P-type fourth semiconductor layer 15 is formed on an inner surface of the fourth recess part 53a so as to generate a fifth recess part 54a being smaller than the fourth recess part 53a; and has a fourth impurity concentration lower than the third impurity concentration. An N-type fifth semiconductor layer 16 is formed on an inner surface of the fifth recess part 54a so as to generate a sixth recess part 55a being smaller than the fifth recess part 54a.
    • 要解决的问题:提供具有高击穿电压的双向恒压二极管。 解决方案:在N型半导体衬底11的第一凹部11c的内表面上形成N型第一半导体层12,以产生小于第一凹部的第二凹部51a。 并且具有比半导体衬底11低的第一杂质浓度.P型第二半导体层13形成在第二凹部51a的内表面上,以便产生比第二凹部小的第三凹部52a 第51a部分; 并具有第二杂质浓度。 在第三凹部52a的内表面上形成P型第三半导体层14,以产生比第三凹部52a小的第四凹部53a。 并且具有高于第二杂质浓度的第三杂质浓度。 在第四凹部53a的内表面上形成P型第四半导体层15,以产生小于第四凹部53a的第五凹部54a; 并且具有比第三杂质浓度低的第四杂质浓度。 N型第五半导体层16形成在第五凹部54a的内表面上,以产生小于第五凹部54a的第六凹部55a。 版权所有(C)2012,JPO&INPIT
    • 3. 发明专利
    • Semiconductor device
    • 半导体器件
    • JP2008300395A
    • 2008-12-11
    • JP2007141668
    • 2007-05-29
    • Toshiba Corp株式会社東芝
    • NOZU TETSUO
    • H01L21/822H01L21/8234H01L27/04H01L27/06H01L27/088H01L29/78
    • H01L23/60H01L27/0255H01L2924/0002H01L2924/00
    • PROBLEM TO BE SOLVED: To provide a semiconductor device that is provided with a protective element having a high area efficiency and high protecting performance.
      SOLUTION: In the semiconductor device 1, an insulation film 3 is formed on a silicon substrate 2, and a silicon film 4 is provided thereon. A lower current route comprised of an N-type area 5, a P-type area 6 and an N-type area 7 is formed in the silicon substrate 2, and an upper current route comprised of an N-type area 8, a P-type part 9 and an N-type part 10 is formed in the silicon film 4. In addition, an N
      - -type area 5b is formed within the N-type area 5. The upper and lower current routes are connected in parallel through contacts 11 and 12, and the lower current route is formed in an area including at least a part of an area immediately under the area where the upper current route is formed. Since the N
      - -type area 5b is interposed in the lower current route, the lower current route is higher in resistance than the upper current route.
      COPYRIGHT: (C)2009,JPO&INPIT
    • 要解决的问题:提供一种具有高面积效率和高保护性能的保护元件的半导体器件。 解决方案:在半导体器件1中,在硅衬底2上形成绝缘膜3,并且在其上提供硅膜4。 在硅衬底2中形成由N型区域5,P型区域6和N型区域7构成的较低电流路径,并且由N型区域8,P 型部分9和N型部分10形成在硅膜4中。此外,在N型区域5内形成有N型区域5b。上部和下部 电流路径通过触点11和12并联连接,并且下电流路径形成在包括形成上电流路径的区域正下方的区域的至少一部分的区域中。 由于N - 型区域5b插入在较低电流路径中,所以较低电流路径的电阻高于上电流路线。 版权所有(C)2009,JPO&INPIT
    • 8. 发明专利
    • INSPECTION PORT FOR MOLECULAR BEAM EPITAXY DEVICE
    • JPH01313387A
    • 1989-12-18
    • JP14042388
    • 1988-06-09
    • TOSHIBA CORP
    • NOZU TETSUO
    • C30B23/08H01L21/203
    • PURPOSE:To accurately measure the temp. of a semiconductor substrate under epitaxial growth without clouding the glass window of the inspection port for a long time by using the title inspection port of specified structure. CONSTITUTION:A rotatable glass disk 5 is provided in a cylinder part 3 having the upper surface 4 and lower surface 2, cylinder parts 1 and 7 connected to the upper surface 4 and lower surface 2 and having a radius smaller than that of the cylinder part 3 are coaxially arranged to form the inspection port 11 having a glass window 8 at one end of the cylinder part 7 connected to the upper surface 4. The inspection port 11 is fixed to a molecular beam epitaxy device 9, a shutter 14 is opened, and the temp. of the substrate 12 is measured by a radiation pyrometer 13, for example, through the inspection port 11. Although the part of the glass disk 5 opposed to the cylinder part 1 is clouded with the lapse of time, a rotating shaft 6 is rotated to face the transparent part of the glass disk 5 toward the cylinder part 1, and observation can be carried out without clouding the glass window 8.
    • 9. 发明专利
    • 半導体装置
    • 半导体器件
    • JP2015056492A
    • 2015-03-23
    • JP2013188480
    • 2013-09-11
    • 株式会社東芝Toshiba Corp
    • NOZU TETSUO
    • H01L29/78H01L21/28H01L29/41H01L29/417
    • H01L29/7827H01L29/4236H01L29/42368H01L29/66666H01L29/66734H01L29/7828
    • 【課題】耐圧の高いトレンチ型MISFETを提供する。【解決手段】半導体装置は、第1導電型の半導体基板を備える。第1導電型の第1の半導体層が半導体基板の第1の面上に設けられる。第1導電型の第2の半導体層が第1の半導体層上に設けられている。複数のゲート電極の一端が第2の半導体層に位置し、他端が第1の半導体層に位置し、複数のゲート電極は第1の方向に延伸する。ゲート絶縁膜は、第1の半導体層とゲート電極との間に設けられている。第1絶縁膜は、第2の半導体層とゲート電極との間に設けられゲート絶縁膜より厚い。第1の電極は、互いに隣接するゲート電極間において他端より浅い位置に設けられ、第1半導体層、第2の半導体層および第1絶縁膜に接している。第2の電極は、半導体基板の第1の半導体層とは反対側に設けられている。【選択図】図1
    • 要解决的问题:提供具有高耐压的沟槽型MISFET。解决方案:半导体器件包括第一导电型半导体衬底。 第一导电型第一半导体层设置在半导体衬底的第一表面上。 第一导电型第二半导体层设置在第一半导体层上。 多个栅电极的一端位于第二半导体层中,另一端位于第一半导体层中,并且多个栅电极沿第一方向延伸。 栅极绝缘膜设置在第一半导体层和教导电极之间。 第一绝缘膜设置在第二半导体层与每个栅电极之间,其厚度大于栅极绝缘膜的厚度。 第一电极设置在相邻栅电极之间比另一端浅的位置处,并且与第一半导体层,第二半导体层和第一绝缘膜接触。 第二电极设置在半导体衬底的与设置第一半导体层的一侧相对的一侧上。
    • 10. 发明专利
    • Semiconductor device and method of manufacturing the same
    • 半导体器件及其制造方法
    • JP2014060298A
    • 2014-04-03
    • JP2012205047
    • 2012-09-18
    • Toshiba Corp株式会社東芝
    • NOZU TETSUO
    • H01L29/78H01L21/336H01L29/06
    • H01L29/78H01L23/48H01L29/0865H01L29/1095H01L29/407H01L29/66477H01L29/66734H01L29/7813H01L2924/0002H01L2924/0001H01L2924/00
    • PROBLEM TO BE SOLVED: To provide a semiconductor device having high resistance characteristics and improved manufacturing yield.SOLUTION: A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer; a first semiconductor region of the first conductivity type provided on the second semiconductor layer; a second semiconductor region of the second conductivity type provided on the second semiconductor layer, being in contact with the first semiconductor region, and having a higher impurity element concentration than the second semiconductor layer; a first electrode being in contact with the first semiconductor region, the second semiconductor layer, and the first semiconductor layer via a first insulating film; a second electrode being in contact with the second semiconductor region via a second insulating film; a third electrode connected to the first semiconductor region and the second semiconductor region; and a fourth electrode electrically connected to the first semiconductor layer.
    • 要解决的问题:提供具有高电阻特性和提高制造成品率的半导体器件。解决方案:一种半导体器件包括:第一导电类型的第一半导体层; 设置在第一半导体层上的第二导电类型的第二半导体层; 设置在第二半导体层上的第一导电类型的第一半导体区域; 第二导电类型的第二半导体区域设置在第二半导体层上,与第一半导体区域接触,并且具有比第二半导体层更高的杂质元素浓度; 经由第一绝缘膜与第一半导体区域,第二半导体层和第一半导体层接触的第一电极; 第二电极经由第二绝缘膜与第二半导体区域接触; 连接到第一半导体区域和第二半导体区域的第三电极; 和与第一半导体层电连接的第四电极。