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1. 发明专利

JP2008218556A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2008218556A
公开(公告)日：2008-09-18
申请号：JP2007051404
申请日：2007-03-01
申请人： Toshiba Corp , 株式会社東芝
发明人： OSAWA TAKASHI
IPC分类号： H01L27/10 , G11C11/404
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L29/7841 , H01L29/785
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device which includes fin-type FETs adopted as memory cells, and arrays of small memory cells. SOLUTION: The semiconductor memory device includes: a plurality of fin-type semiconductors extending in a first direction; a source layer S and a drain layer D formed in each of the fin-type semiconductors; a body B which is formed in the part of fin-type semiconductor that is located between the source layer and the drain layer, is electrically afloat, and accumulates or discharges a number of carriers for data storage; a first gate electrode G1 formed in a first slot lying between adjacent two fin-type semiconductors; a second gate electrode G2 which is adjacent to the first slot and is formed in a second slot lying between adjacent two fin-type semiconductors; a bit line BL connected to the drain layer and extended in the first direction; a word line WL connected to the first gate electrode and extended a second direction perpendicular to the first direction; and a source line SL connected to the source layer S and extended in a second direction. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体存储器件，其包括作为存储单元采用的鳍式FET，以及小存储单元的阵列。解决方案：半导体存储器件包括：沿第一方向延伸的多个鳍型半导体; 形成在每个翅片型半导体中的源极层S和漏极层D; 形成在位于源极层和漏极层之间的鳍状半导体的一部分中的主体B电浮动，并且累积或放出多个用于数据存储的载体; 形成在位于相邻的两个鳍式半导体之间的第一槽中的第一栅电极G1; 第二栅电极G2，其与第一槽相邻，并且形成在位于相邻的两个鳍型半导体之间的第二槽中; 连接到漏极层并沿第一方向延伸的位线BL; 连接到所述第一栅极的字线WL，并延伸垂直于所述第一方向的第二方向; 以及连接到源极层S并沿第二方向延伸的源极线SL。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2006252658A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2006252658A
公开(公告)日：2006-09-21
申请号：JP2005067296
申请日：2005-03-10
申请人： Toshiba Corp , 株式会社東芝
发明人： FUJITA KATSUYUKI , OSAWA TAKASHI
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which generation of malfunction of a sense amplifier circuit can be prevented. SOLUTION: The semiconductor memory device is provided with: memory cells nc which are connected to a plurality of bit lines BL; memory cells ncb which are connected to a plurality of bit lines bBL; a plurality of sense amplifier circuits which are provided for every bit line to read the data of the memory cells, and provided with a load circuits LDC which are respectively connected to a power supply voltage terminal, the bit lines and dummy bit lines to generate a reference current and to provide the current to the dummy bit lines and the bit lines, and latch circuits LT which are connected to sense amplifier driving lines SA and bSA to control driving and hold the reference current by comparing the potentials of the bit lines and the potentials of the dummy bit lines. A sense amplifier driving circuit controls the potential of the sense amplifier driving line by receiving a sense operation control signal and the potentials of the sense amplifier driving lines SA and bSA are complementarily reversed when the initial potential difference detecting operation is switched to a latter latch operation in the sense amplifier circuit. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供可以防止读出放大器电路发生故障的半导体存储器件。解决方案：半导体存储器件设置有：连接到多个位线BL的存储单元nc; 连接到多个位线bBL的存储单元ncb; 多个读出放大器电路，被提供用于每个位线以读取存储单元的数据，并且设置有分别连接到电源电压端子，位线和虚拟位线的负载电路LDC，以产生参考电流，并将电流提供给虚拟位线和位线，以及与读出放大器驱动线SA和bSA连接的锁存电路LT，以通过比较位线的电位和虚拟位线的电位。读出放大器驱动电路通过接收感测操作控制信号来控制读出放大器驱动线的电位，并且当初始电位差检测操作切换到后一个锁存操作时，读出放大器驱动线SA和bSA的电位互补地反转在感测放大器电路中。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2006139856A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2006139856A
公开(公告)日：2006-06-01
申请号：JP2004328658
申请日：2004-11-12
申请人： Toshiba Corp , 株式会社東芝
发明人： FUJITA KATSUYUKI , OSAWA TAKASHI
IPC分类号： G11C29/04 , G11C11/401 , G11C11/404 , H01L21/8242 , H01L27/108
CPC分类号： H01L29/7841
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device that can improve the production yield.
SOLUTION: The device has at least one redundancy word line that is disposed along a row direction in a memory cell array, and includes a redundancy memory cell for relieving a defective memory cell; a redundancy determining circuit that compares between an externally given row address and a row address of a defective memory cell address that is stored previously internally; and when both the row addresses coincide with each other, activates a redundancy row decoder, and performs predetermined address conversion on the row address to output the row address; and the redundancy row decoder that selects the desired redundancy word line, based on the row address given by the redundancy determination circuit.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供可以提高生产率的半导体存储装置。解决方案：该装置具有沿着存储单元阵列中的行方向布置的至少一个冗余字线，并且包括用于缓解有缺陷的存储单元的冗余存储单元; 冗余确定电路，用于在外部给定的行地址和先前存储的缺陷存储器单元地址的行地址之间进行比较; 并且当两个行地址彼此一致时，激活冗余行解码器，并且对行地址执行预定地址转换以输出行地址; 以及冗余行解码器，其基于由冗余确定电路给出的行地址来选择期望的冗余字线。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2006108309A Semiconductor memory device and driving method of fbc memory cell 有权
标题翻译： FBC记忆体的半导体存储器件和驱动方法
公开(公告)号：JP2006108309A
公开(公告)日：2006-04-20
申请号：JP2004291609
申请日：2004-10-04
申请人： Toshiba Corp , 株式会社東芝
发明人： OSAWA TAKASHI
IPC分类号： H01L27/108 , G11C11/407 , G11C14/00 , H01L21/8242 , H01L29/786
CPC分类号： G11C8/14 , G11C11/4085 , G11C2211/4016 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/115 , H01L27/1203 , H01L29/7841
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of suppressing degradation in data-holding ability, and fully micronizing its structure.
SOLUTION: The semiconductor memory device comprises a semiconductor substrate 10, comprising a semiconductor film SOI on a first insulating film BOX; a memory cell MC which stores data by charging/discharging the electric charges from a body region FB formed in the semiconductor film SOI, and comprises a source layer S and a drain layer D on both sides; a second insulating film GI on the body region FB; a first word line WL above the film; a bit line BL which is connected to the drain layer D and serves as a reference potential, when the memory cell MC is in data-holding state; a source line SL which is connected to the source line S and serves as a reference potential; and a second word line BWL which is embedded in the first insulating film BOX, below the body region FB of memory cell MC. Electric potential V
BWLH of the second word line BWL, when it is in data-holding state, is closer to the reference potential than to the potential V
BWLL of the second word line BWL, when reading/writing data.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够抑制数据保持能力的劣化并使其结构完全微细化的半导体存储器件。解决方案：半导体存储器件包括半导体衬底10，其包括在第一绝缘膜BOX上的半导体膜SOI; 存储单元MC，其通过从形成在半导体膜SOI中的体区FB充电/放电来存储数据，并且在两侧包括源极层S和漏极层D; 身体区域FB上的第二绝缘膜GI; 电影上方的第一个字线WL; 当存储单元MC处于数据保持状态时，连接到漏极层D并用作基准电位的位线BL; 源极线SL，其连接到源极线S并用作参考电位; 以及嵌入在第一绝缘膜BOX中的第二字线BWL，位于存储单元MC的体区FB的下方。当处于数据保持状态时，第二字线BWL的电位V SB SBLH 比第二字的电位V SBLLL 更接近参考电位行BWL，读/写数据时。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2006040421A Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：JP2006040421A
公开(公告)日：2006-02-09
申请号：JP2004219783
申请日：2004-07-28
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： HIGASHI TOMOKI , OSAWA TAKASHI
IPC分类号： G11C29/12
CPC分类号： G11C11/404 , G11C11/4094 , G11C29/50 , G11C2211/4016
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device of which the memory cell characteristic can be evaluated externally without through a write-in driver or a sense amplifier.
SOLUTION: The semiconductor storage device is provided with a cell array CA with memory cells, word lines WL, sub-bit lines SBL, a bit selection circuit 10 for selecting a sub-bit line, a main bit line MBL connected to the selected sub-bit line, a sense units SU for reading data through the main bit line, a write-in driver WD for writing data through the main bit line, and switching elements SWA which are connected across the main bit lines and a pad P1 and are turned on when detecting potential of a sub-bit line externally through the pad P1 without using a sense unit, or when applying voltage to the sub-bit line externally through the pad P1 without using the write-in driver.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体存储装置，其中可以通过写入驱动器或读出放大器在外部评估存储单元特性。解决方案：半导体存储装置设有具有存储单元的单元阵列CA，字线WL，子位线SBL，用于选择子位线的位选择电路10，连接到所选择的子位线，用于通过主位线读取数据的感测单元SU，用于通过主位线写入数据的写入驱动器WD和跨主位线连接的开关元件SWA和衬垫 P1，并且在不使用感测单元的情况下检测到通过焊盘P1的外部的子位线的电位，或者在不使用写入驱动器的情况下通过焊盘P1向外部施加电压到子位线时，导通。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2005332495A Semiconductor memory apparatus 有权
标题翻译：半导体存储器
公开(公告)号：JP2005332495A
公开(公告)日：2005-12-02
申请号：JP2004150492
申请日：2004-05-20
申请人： Toshiba Corp , 株式会社東芝
发明人： OSAWA TAKASHI
IPC分类号： H01L27/108 , G11C5/00 , G11C7/00 , G11C7/02 , G11C11/14 , G11C11/401 , G11C11/404 , H01L21/8242 , H01L29/786
CPC分类号： G11C11/14 , H01L29/7841
摘要： PROBLEM TO BE SOLVED: To perform write-in by switching continuously a column address while suppressing current consumption.
SOLUTION: This semiconductor memory apparatus is provided with a memory cell array in which memory cells in each of which write-in is performed by making a cell current flow are arranged in a matrix state, word lines provided in parallel to a row direction in the memory cell array, bit lines provided in parallel to a column direction being a direction crossing the row direction, a sense amplifier connected to each of bit lines and writing held data in the memory cell, a data line supplying data to be written in the sense amplifier, and a control circuit controlling so that the connection of the sense amplifier and the bit line is intercepted while data to be written is held by the memory cell through the data line at continuous write-in operation in which a column address selecting a column is switched continuously and write-in is performed, after data are held by the sense amplifier, the connection of one part of the sense amplifier and the bit line is opened, and data held by the sense amplifier are written in the memory cell.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过在抑制电流消耗的同时连续切换列地址来执行写入。解决方案：该半导体存储装置设置有存储单元阵列，其中通过使单元电流流动而执行每个写入的存储单元以矩阵状排列，并行设置的字线存储单元阵列中的方向，与列方向平行设置的位线是与行方向交叉的方向，连接到每个位线的读出放大器和将保存的数据写入存储单元的数据线，提供要写入的数据的数据线在读出放大器中，以及控制电路，以便在连续写入操作下，由存储器单元通过数据线保持读写放大器与位线的连接而被写入的数据被保持，其中列地址选择列被连续地切换并且在读出放大器保持数据之后执行写入，打开读出放大器和位线的一部分的连接，并且由读出放大器被写入存储单元。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2005302077A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2005302077A
公开(公告)日：2005-10-27
申请号：JP2004112229
申请日：2004-04-06
申请人： Toshiba Corp , 株式会社東芝
发明人： OSAWA TAKASHI
IPC分类号： G11C11/409 , G11C7/06 , G11C8/00 , G11C11/404 , G11C11/4091
CPC分类号： G11C11/4091 , G11C7/065 , G11C11/404 , G11C2207/005 , G11C2207/065
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of preventing a charge pumping phenomenon of an FBC memory with low power consumption.
SOLUTION: The semiconductor memory device 100 is provided with a sense amplifier which is a sense amplifier 10 connected to a first bit line BBL0 and a second bit line BBLL0, includes a cross couple CCP including switching elements TCP1, TCP2 serially connected between the first and the second bit lines and a cross couple CCN including switching elements TCN1, TCN2 serially connected between the first and second bit lines, in which a node NP between the two swtiching elements of the cross couple CCP is connected with power sources SAP, VBLH via a plurality of paths, a node NN between the two switching elements of the cross couple CCN is also connected with power sources BSAN, VBLL via a plurality of paths and which selects a path based on potential of a column selection line.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供能够防止低功耗的FBC存储器的电荷泵送现象的半导体存储器件。解决方案：半导体存储器件100设置有读出放大器，读出放大器是连接到第一位线BBL0和第二位线BBLL0的读出放大器10，包括交叉耦合CCP，其包括串行连接在第一位线和第二位线以及交叉耦合CCN，包括串联连接在第一和第二位线之间的开关元件TCN1，TCN2，其中交叉耦合CCP的两个开关元件之间的节点NP与电源SAP连接， VBLH通过多个路径，交叉耦合CCN的两个开关元件之间的节点NN也经由多个路径与电源BSAN，VBLL连接，并且基于列选择线的电位来选择路径。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2005277435A Semiconductor device and manufacturing method therefor 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005277435A
公开(公告)日：2005-10-06
申请号：JP2005136211
申请日：2005-05-09
申请人： Toshiba Corp , 株式会社東芝
发明人： KOYAMA HIROSUKE , OSAWA TAKASHI , SAWADA SHIZUO
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8242 , H01L27/108 , H01L29/417 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method which can prevent short circuiting of contacts and wirings, where the contacts can be formed self-aligned, the thickness of the film formed on the wiring can be certainly controlled, fine contacts can be formed, the yield of contact aperture is high, and the contact is easily embedded.
SOLUTION: Wiring L, formed on a first insulating film 1, comprises a conductive film 2, a silicon oxide film 3 and a silicon nitride film 4. The insulating film 5 is planarized so as to be adjusted to be the same height as that of the upper surface of the silicon nitride film 4. By the silicon nitride film 4 of the wiring L and a photoresist formed by using the contact pattern in the shape of line/space, a plurality of contact holes CH are formed in the insulating film 5. In a sidewall of the contact holes CH, a sidewall spacer 7a comprising the insulating film 7 is formed.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供能够防止触点形成自对准的触点和布线短路的半导体器件及其制造方法，可以可靠地控制形成在布线上的膜的厚度可以形成微细的接触，接触孔的收率高，接触容易嵌入。解决方案：形成在第一绝缘膜1上的布线L包括导电膜2，氧化硅膜3和氮化硅膜4.绝缘膜5被平坦化以被调节为相同的高度与氮化硅膜4的上表面相同。通过布线L的氮化硅膜4和利用线/空间形状的接触图形形成的光致抗蚀剂，形成多个接触孔CH 绝缘膜5.在接触孔CH的侧壁中，形成包括绝缘膜7的侧壁间隔物7a。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2005108341A Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：JP2005108341A
公开(公告)日：2005-04-21
申请号：JP2003341533
申请日：2003-09-30
申请人： Toshiba Corp , 株式会社東芝
发明人： OSAWA TAKASHI
IPC分类号： H01L27/10 , G11C7/06 , G11C7/12 , G11C7/14 , G11C11/401 , G11C11/404 , G11C11/409 , G11C11/4091 , G11C11/4094 , G11C11/56 , H01L21/8242 , H01L27/108
CPC分类号： G11C11/4091 , G11C7/062 , G11C7/12 , G11C7/14 , G11C11/4094 , H01L27/108 , H01L29/7841
摘要： PROBLEM TO BE SOLVED: To accurately discriminate data "1" or "0" in reading the data from an FBC.
SOLUTION: The device is equipped with a sense amplifier 11, a latch circuit 22 for latching output for the sense amplifier 11, a read control circuit 23, a write control circuit 24, a reference potential generation circuit 12 connected to a reference bit line RBL, a high potential setting transistor 25 for setting a selective reference bit line RBL as the output for the reference potential generation circuit 12 to potential "1", and a midpoint potential setting transistor 26 for setting the selective reference bit line RBL to the midpoint potential. Because logic for the data is decided by writing the midpoint potential on a reference cell 13 in advance and comparing the data read from selected FBC1 with the data read from the reference cell 13, the reference cell 13 for the data "1" and the reference cell 13 for the data "0" are not required to be individually arranged. Because configuration for the circuit can be simplified and mirror rate for a current mirror circuit inside the sense amplifier 11 can be set to 1, size for the circuit can be reduced.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：在从FBC读取数据时准确地区分数据“1”或“0”。解决方案：该器件配备有读出放大器11，用于锁存读出放大器11的输出的锁存电路22，读控制电路23，写控制电路24，连接到参考的参考电位产生电路12 位线RBL，用于将选择性基准位线RBL设定为基准电位产生电路12的输出为电位“1”的高电位设定晶体管25以及用于将选择性基准位线RBL设定为中点电位设定晶体管26 中点潜力。由于数据的逻辑是通过预先在参考单元13上写入中点电位并将从选择的FBC1读取的数据与从参考单元13读取的数据进行比较来确定的，所以用于数据“1”的参考单元13和参考单元13 数据“0”的单元13不需要单独排列。由于电路的配置可以简化，读出放大器11内部的电流镜像电路的镜像速率可以设置为1，所以可以减小电路的尺寸。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2005026366A Semiconductor memory device and semiconductor integrated circuit 有权
标题翻译：半导体存储器件和半导体集成电路
公开(公告)号：JP2005026366A
公开(公告)日：2005-01-27
申请号：JP2003188539
申请日：2003-06-30
申请人： Toshiba Corp , 株式会社東芝
发明人： OSAWA TAKASHI
IPC分类号： H01L27/108 , H01L21/8242 , H01L21/84 , H01L27/01 , H01L27/105 , H01L27/12 , H01L29/76 , H01L31/0392
CPC分类号： H01L27/108 , H01L21/84 , H01L27/105 , H01L27/10823 , H01L27/10894 , H01L27/1203 , H01L29/7841
摘要： PROBLEM TO BE SOLVED: To provide a vertical transistor in which parasitic resistance of a source is small and which is not influenced by "1" disturbance by a parasitic bipolar element.
SOLUTION: This semiconductor memory device includes an FBC 2 made of the vertical transistor disposed in a matrix form on an SOI substrate 1, and a metal layer 4 formed between a buried oxide film 3 of the SOI substrate 1 and the FBC 2. Since the metal layer 4 is formed between the FBC 2 and the buried oxide film 3, the parasitic resistance of a source can be reduced, the transistor is not influenced by the "1" disturbance by the parasitic bipolar element, and the FBC 2 having good characteristics is obtained.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种垂直晶体管，其中源极的寄生电阻较小并且不受寄生双极元件的“1”干扰的影响。解决方案：该半导体存储器件包括由SOI衬底1上以矩阵形式设置的垂直晶体管制成的FBC 2，以及形成在SOI衬底1的埋入氧化物膜3和FBC2之间的金属层4 由于金属层4形成在FBC 2和埋入氧化物膜3之间，因此源极的寄生电阻可以降低，晶体管不受寄生双极元件的“1”干扰的影响，FBC2 获得了良好的特性。版权所有（C）2005，JPO＆NCIPI

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