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1. 发明专利

JP2006100406A Manufacturing method of soi wafer 审中-公开
标题翻译： SOI WAFER的制造方法
公开(公告)号：JP2006100406A
公开(公告)日：2006-04-13
申请号：JP2004282267
申请日：2004-09-28
申请人： Toshiba Ceramics Co Ltd , 東芝セラミックス株式会社
发明人： INOUE KENJI
IPC分类号： H01L27/12 , H01L21/02 , H01L21/304
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of an SOI wafer which improves a process yield and uniformizes an active layer thickness within a field.
SOLUTION: An element board of 150 mm in diameter and a supporting board are prepared respectively so that wet oxidation is carried out to an element board so as to form an oxide film of 1 μm thickness. The surface side to be polished of the element board wherein the oxide film is formed, and the polished surface of a supporting board, are superposed and contacted closely. Heat treatment is performed to the closely contacted joined substrates under high temperature of 1,000°C so as to reinforce the junction force of the superposed surfaces. Then, it is made to reduce to 125 mm in diameter. After removing the oxide film formed by carrying out fluoric acid processing at the time of heat treatment, grinding and primary polish are made for the surface. After generating perimeter sagging in the periphery of the range (region) of 2 mm from the end face (outermost periphery) of the joined substrates, once again, it is made to reduce to 100 mm in diameter by chamfering work. Finally, secondary polish and finishing polish are made so as to produce the SOI wafer.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种SOI晶片的制造方法，其提高了工艺成品率并使场内的有源层厚度均匀化。解决方案：分别制备直径为150mm的元件板和支撑板，以便对元件板进行湿式氧化，以形成1μm厚的氧化膜。其中形成氧化膜的元件板的抛光表面侧和支撑板的抛光表面被重叠并紧密接触。在1000℃的高温下对紧密接合的接合基板进行热处理，以加强叠置表面的接合力。然后，使其直径减小到125mm。在热处理后除去通过进行氟酸处理而形成的氧化膜之后，对表面进行研磨和初级抛光。在接合基板的端面（最外周）的2mm的范围（区域）的周边产生周边下垂之后，通过倒角加工再次使其直径减小到100mm。最后，进行二次抛光和抛光抛光以制造SOI晶片。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2000062891A PACKAGE BODY FOR SEMICONDUCTOR WAFER 失效
公开(公告)号：JP2000062891A
公开(公告)日：2000-02-29
申请号：JP22723498
申请日：1998-08-11
申请人： TOSHIBA CERAMICS CO
发明人： KUROKI TOMOHITO , KOBAYASHI SHIN , INOUE KENJI
IPC分类号： B65D85/86 , H01L21/673 , H01L21/68
摘要： PROBLEM TO BE SOLVED: To enable pressure in a wafer case during air transportation to be restored promptly after landing by providing a bag for packaging a wafer case with semiconductor wafers housed therein, and setting in a specific range the ratio of a value in which the volume of semiconductor wafers is subtracted from the content volume of the bag and the content volume of the wafer case. SOLUTION: The wafer case 3 for a semiconductor wafer packaging body 1 is comprised of a case main body 5 and a lid body 7. A bag 4 for packaging this wafer case 3 is provided with an opening for putting in and out the wafer case 3 at its one side. In this case, regarding the size of the wafer case 3 and the bag 4, the ratio of a value in which the volume of the semiconductor is subtracted from the content volume of the bag 4 and the content volume of the wafer case 3 is set to be in a range of 1.03-1.18. By this structure, even in the case where if the atmosphere in the airplane lowers during air- transportation and thereby air in the wafer case 3 comes out of the bag 4, the pressure in the wafer case 3 is maintained on the order of 0.9 atm, so that the pressure in the water case can be restored promptly to the atmosphere after landing.

3. 发明专利

JP2004140077A Semiconductor substrate thermal treatment furnace 审中-公开
公开(公告)号：JP2004140077A
公开(公告)日：2004-05-13
申请号：JP2002301728
申请日：2002-10-16
申请人： Toshiba Ceramics Co Ltd , 東芝セラミックス株式会社
发明人： INOUE KENJI
IPC分类号： H01L21/22 , H01L21/31
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor substrate thermal treatment furnace which is capable of uniformly forming a film on the surface of a semiconductor substrate.
SOLUTION: The semiconductor substrate thermal treatment furnace is equipped with a furnace core pipe 3 where a semiconductor substrate boat 2 mounted with the semiconductor substrates W is housed and a gas injection nozzle 4 which injects process gas into the furnace core pipe 3. The gas injection nozzle 4 is equipped with, at least, two gas injection ports 4u and 4b which are arranged in a vertical direction.
COPYRIGHT: (C)2004,JPO

4. 发明专利

JP2007214256A Soi wafer 审中-公开
标题翻译： SOI WAFER
公开(公告)号：JP2007214256A
公开(公告)日：2007-08-23
申请号：JP2006030945
申请日：2006-02-08
申请人： Toshiba Ceramics Co Ltd , 東芝セラミックス株式会社
发明人： INOUE KENJI
IPC分类号： H01L21/02 , B24B9/00 , H01L21/304 , H01L27/12
摘要： PROBLEM TO BE SOLVED: To provide an SOI wafer wherein the deficiency of an SOI layer around the outer periphery of a wafer can be prevented easily and conveniently when manufacturing a semiconductor device.
SOLUTION: An SOI wafer 10 is provided with a wafer 11 for a supporting board, a joint insulation film 12 on its surface, and an SOI layer 13. The outer periphery of the SOI wafer 10 is beveled, and a wafer end face 14, a bevel face 15 on the side of the SOI layer 13, and a bevel face 16 on the side of the wafer 11 for a supporting board are provided around the outer periphery thereof. A bevel angle θ of the bevel face 15 to the surface of the SOI layer 13 is set to 30-60 degrees. Thus, the manufacture yield of the SOI wafer can be stabilized without reduction, and the deficiency of the SOI layer 13 around its outer periphery can be prevented easily and conveniently in the manufacturing step of a semiconductor device using the SOI wafer.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种SOI晶片，其中当制造半导体器件时，可以容易且方便地防止在晶片的外周周围的SOI层的不足。解决方案：SOI晶片10设置有用于支撑板的晶片11，其表面上的接合绝缘膜12和SOI层13. SOI晶片10的外周是倾斜的，并且晶片端面14，SOI层13侧的斜面15以及用于支撑板的晶片11侧的斜面16设置在其外周。斜面15与SOI层13的表面的斜角θ设定为30-60度。因此，SOI晶片的制造成品率可以稳定而不会降低，并且在使用SOI晶片的半导体器件的制造步骤中可以容易且方便地防止SOI层13在其外周周围的不足。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2007214255A Method of manufacturing laminated soi wafer 审中-公开
标题翻译：制造层压SOI波形的方法
公开(公告)号：JP2007214255A
公开(公告)日：2007-08-23
申请号：JP2006030944
申请日：2006-02-08
申请人： Toshiba Ceramics Co Ltd , 東芝セラミックス株式会社
发明人： INOUE KENJI
IPC分类号： H01L21/02 , H01L27/12
摘要： PROBLEM TO BE SOLVED: To make the SOI layer of an SOI wafer large as much as possible and to easily and conveniently prevent a wafer for a supporting board on its rear surface from being damaged, when manufacturing a laminated SOI wafer. SOLUTION: A wafer 11 for a supporting board and a wafer 12 for an active layer are thermally oxidized to form a protective oxide film 13 and a bonding oxide film 14. Then, the surface of the wafer 11 for a supporting board is mirror-polished to high flatness, and the surface of the wafer 11 for a supporting board and the wafer 12 for an active layer are bonded with the bonding oxide layer 14 in-between. Furthermore, the outer periphery of the laminated wafer is ground, an SOI layer 15 is formed by thin film processing, and bevel faces 16 and 17 are formed around the outer periphery of the wafer by bevel processing, mirror-polishing, etc. Finally, the protective oxide film 13 is removed by etching to complete a laminated SOI wafer product. Thus, the rear surface of the SOI wafer is protected by the protective oxide film 13 through the SOI wafer manufacture. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了使SOI晶片的SOI层尽可能大，并且容易且方便地防止其后表面上的支撑板的晶片被损坏时，制造叠层SOI晶片时。解决方案：用于支撑板的晶片11和用于有源层的晶片12被热氧化以形成保护氧化膜13和接合氧化膜14.然后，用于支撑板的晶片11的表面是镜面抛光到高平坦度，并且用于支撑板的晶片11的表面和用于有源层的晶片12在其间结合有接合氧化物层14。此外，对层叠晶片的外周进行研磨，通过薄膜加工形成SOI层15，通过斜面加工，镜面抛光等在晶片的外周形成斜面16,17。通过蚀刻去除保护氧化膜13，以完成层叠的SOI晶片产品。因此，SOI晶片的后表面通过SOI晶片制造被保护氧化膜13保护。版权所有（C）2007，JPO＆INPIT

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