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1. 发明公开

EP2684124A2 SHORT POINTERS 审中-公开
标题翻译：速记
公开(公告)号：EP2684124A2
公开(公告)日：2014-01-15
申请号：EP12712362.8
申请日：2012-03-08
申请人： Telefonaktiebolaget L M Ericsson (PUBL)
发明人： MEIER, Stephan , FAVOR, John G. , GEWIRTZ, Evan , HATHAWAY, Robert , TREHUS, Eric
IPC分类号： G06F9/30 , G06F9/34
CPC分类号： G06F9/30043 , G06F9/342
摘要： A digital processor stores pointers of different sizes in memory. The processor, specifically, executes instructions to store a long or short pointer. Long pointers reference any address in the memory's logical address space, while short pointers merely reference any address in a subset of that space. However, short pointers are smaller in size as stored in memory than long pointers. Long pointers thus support relatively large address range capabilities, while short pointers use less memory. The processor also executes instructions to load a long or short pointer into the register file, and does so in a way that does not require the processor to distinguish between the different pointers when executing other instructions. Specifically, the processor converts long and short pointers into a common format for loading into the register file, and converts pointers in the common format back into long or short pointers for storing in the memory.

2. 发明公开

EP2569696A1 HIERARCHICAL MULTITHREADED PROCESSING 审中-公开
标题翻译：分层多线程处理
公开(公告)号：EP2569696A1
公开(公告)日：2013-03-20
申请号：EP11725198.3
申请日：2011-04-21
申请人： Telefonaktiebolaget L M Ericsson (PUBL)
发明人： GEWIRTZ, Evan , HATHAWAY, Robert , MEIER, Stephan , HO, Edward
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3802
摘要： In one embodiment, a current candidate thread is selected from each of multiple first groups of threads using a low granularity selection scheme, where each of the first groups includes multiple threads and first groups are mutually exclusive. A second group of threads is formed comprising the current candidate thread selected from each of the first groups of threads. A current winning thread is selected from the second group of threads using a high granularity selection scheme. An instruction is fetched from a memory based on a fetch address for a next instruction of the current winning thread. The instruction is then dispatched to one of the execution units for execution, whereby execution stalls of the execution units are reduced by fetching instructions based on the low granularity and high granularity selection schemes.

3. 发明申请

WO2012123866A3 SHORT AND LONG POINTERS 审中-公开
公开(公告)号：WO2012123866A3
公开(公告)日：2012-09-20
申请号：PCT/IB2012/051099
申请日：2012-03-08
申请人： TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) , MEIER, Stephan , FAVOR, John G. , GEWIRTZ, Evan , HATHAWAY, Robert , TREHUS, Eric
发明人： MEIER, Stephan , FAVOR, John G. , GEWIRTZ, Evan , HATHAWAY, Robert , TREHUS, Eric
IPC分类号： G06F9/30 , G06F9/34
摘要： A digital processor stores pointers of different sizes in memory. The processor, specifically, executes instructions to store a long or short pointer. Long pointers reference any address in the memory's logical address space, while short pointers merely reference any address in a subset of that space. However, short pointers are smaller in size as stored in memory than long pointers. Long pointers thus support relatively large address range capabilities, while short pointers use less memory. The processor also executes instructions to load a long or short pointer into the register file, and does so in a way that does not require the processor to distinguish between the different pointers when executing other instructions. Specifically, the processor converts long and short pointers into a common format for loading into the register file, and converts pointers in the common format back into long or short pointers for storing in the memory.

4. 发明申请

WO2011141837A1 HIERARCHICAL MULTITHREADED PROCESSING 审中-公开
标题翻译：分层多元处理
公开(公告)号：WO2011141837A1
公开(公告)日：2011-11-17
申请号：PCT/IB2011/051762
申请日：2011-04-21
申请人： TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) , GEWIRTZ, Evan , HATHAWAY, Robert , MEIER, Stephan , HO, Edward
发明人： GEWIRTZ, Evan , HATHAWAY, Robert , MEIER, Stephan , HO, Edward
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3802
摘要： In one embodiment, a current candidate thread is selected from each of multiple first groups of threads using a low granularity selection scheme, where each of the first groups includes multiple threads and first groups are mutually exclusive. A second group of threads is formed comprising the current candidate thread selected from each of the first groups of threads. A current winning thread is selected from the second group of threads using a high granularity selection scheme. An instruction is fetched from a memory based on a fetch address for a next instruction of the current winning thread. The instruction is then dispatched to one of the execution units for execution, whereby execution stalls of the execution units are reduced by fetching instructions based on the low granularity and high granularity selection schemes.
摘要翻译：在一个实施例中，使用低粒度选择方案从多个第一组线程中选择当前候选线程，其中每个第一组包括多个线程，并且第一组是互斥的。形成第二组线程，包括从第一组线程中选择的当前候选线程。使用高粒度选择方案从第二组线程中选择当前获胜线程。基于当前获胜线程的下一条指令的获取地址从存储器中取出指令。然后将指令分派到一个执行单元进行执行，由此通过基于低粒度和高粒度选择方案获取指令来减少执行单元的执行停顿。

5. 发明申请

WO2014102646A1 ATOMIC WRITE AND READ MICROPROCESSOR INSTRUCTIONS 审中-公开
标题翻译：原子写入和阅读微处理器说明书
公开(公告)号：WO2014102646A1
公开(公告)日：2014-07-03
申请号：PCT/IB2013/060888
申请日：2013-12-12
申请人： TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
发明人： GEWIRTZ, Evan , HATHAWAY, Robert , HO, Edward , MEIER, Stephan
IPC分类号： G06F9/30 , G06F9/38 , G06F15/78
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/3834
摘要： Methods and apparatus for performing an atomic hardware operation (HWOP) instruction. According to a method in a computer processor coupled to a memory, the method includes fetching, decoding, and executing the atomic HWOP instruction. The instruction includes a source operand indicating a source location and a destination operand indicating a destination location, wherein each of the source location and the destination location is either a register of the computer processor or an address of the memory. Executing the atomic HWOP instruction includes sending a message to an external agent to cause the external agent to atomically access a set of one or more memory locations of the memory based upon a value stored at the source location, and return a result obtained from said atomic access of the set of memory locations to the destination location. The external agent is external to the computer processor.
摘要翻译：用于执行原子硬件操作（HWOP）指令的方法和装置。根据耦合到存储器的计算机处理器中的方法，该方法包括获取，解码和执行原子HWOP指令。指令包括指示源位置的源操作数和指示目的地位置的目的地操作数，其中源位置和目的地位置中的每一个是计算机处理器的寄存器或存储器的地址。执行原子HWOP指令包括向外部代理发送消息以使得外部代理基于存储在源位置处的值来原子访问存储器的一个或多个存储器位置的集合，并且返回从所述原子获得的结果将存储器位置集合存取到目标位置。外部代理在计算机处理器外部。

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