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1. 发明申请

WO2009131569A1 CONFIGURABLE IC WITH PACKET SWITCH CONFIGURATION NETWORK 审中-公开
标题翻译：可配置IC与分组开关配置网络
公开(公告)号：WO2009131569A1
公开(公告)日：2009-10-29
申请号：PCT/US2008/061074
申请日：2008-04-21
申请人： TABULA, INC. , REDGRAVE, Jason , KHUBCHANDANI, Teju , HUTCHINGS, Brad , TEIG, Steven , SCHMIT, Herman
发明人： REDGRAVE, Jason , KHUBCHANDANI, Teju , HUTCHINGS, Brad , TEIG, Steven , SCHMIT, Herman
IPC分类号： H03K19/173
CPC分类号： H03K19/17776 , G06F17/5054 , H03K19/17736 , H03K19/17752 , H03K19/17756 , H03K19/17764
摘要： Some embodiments of the invention provide configurable integrated circuit (IC) that includes several configurable circuits that are conceptually in tiles. The IC also includes a first data network for passing data between the configurable circuits. The IC further includes a second packet-switch network for receiving packets of data from the outside of the configurable IC and switchably routing each packet to at least one destination tile. In some embodiments, the second packet-switch network supplies data from the tiles that the configurable circuits output in response to data packets received from outside of the configurable IC. Also, in some embodiments, a particular packet that is for a particular resource in a particular tile includes a first address that identifies the particular configurable tile from the plurality of configurable tiles, and then a second address that identifies the particular resource within the particular configurable tile.
摘要翻译：本发明的一些实施例提供了可配置集成电路（IC），其包括概念上在瓦片中的几个可配置电路。 IC还包括用于在可配置电路之间传递数据的第一数据网络。 IC还包括第二分组交换网络，用于从可配置IC的外部接收数据分组，并且可切换地将每个分组路由到至少一个目的地分块。在一些实施例中，第二分组交换网络响应于从可配置IC的外部接收的数据分组提供可配置电路输出的瓦片中的数据。此外，在一些实施例中，用于特定瓦片中的特定资源的特定分组包括识别来自多个可配置分块的特定可配置分块的第一地址，然后标识特定可配置分组内的特定资源的第二地址瓦。

2. 发明申请

WO2008115243A2 CONFIGURABLE IC HAVING A ROUTING FABRIC WITH STORAGE ELEMENTS 审中-公开
标题翻译：具有存储元件的布线布的可配置IC
公开(公告)号：WO2008115243A2
公开(公告)日：2008-09-25
申请号：PCT/US2007/069831
申请日：2007-05-27
申请人： TABULA, INC. , TEIG, Steven , SCHMIT, Herman , REDGRAVE, Jason , HUANG, Randy, Renfu
发明人： TEIG, Steven , SCHMIT, Herman , REDGRAVE, Jason , HUANG, Randy, Renfu
IPC分类号： H03K19/177
CPC分类号： H03K19/17704 , H03K19/17736
摘要： Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.
摘要翻译：一些实施例提供了一种可配置IC，其包括具有存储元件的可配置路由结构。在一些实施例中，路由结构提供将信号路由到来自源和目的地组件的信号通路。一些实施例的路由结构提供了选择性地将通过路由结构的信号存储在路由结构的存储元件内的能力。以这种方式，源或目的地组件连续地执行操作（例如，计算或路由），而不管来自或来自这种组件的先前信号是否存储在路由结构内。源和目标组件包括可配置逻辑电路，可配置互连电路以及在整个可配置IC中接收或分配信号的各种其他电路。

3. 发明申请

WO2009039462A1 METHOD AND SYSTEM FOR REPORTING ON A PRIMARY CIRCUIT STRUCTURE OF AN INTEGRATED CIRCUIT (IC) USING A SECONDARY CIRCUIT STRUCTURE OF THE IC 审中-公开
标题翻译：使用IC的二次电路结构报告集成电路（IC）的主电路结构的方法和系统
公开(公告)号：WO2009039462A1
公开(公告)日：2009-03-26
申请号：PCT/US2008/077141
申请日：2008-09-19
申请人： TABULA, INC. , MILLER, Marc , TEIG, Steven , REDGRAVE, Jason , HUTCHINGS, Brad , THOM, Danny
发明人： MILLER, Marc , TEIG, Steven , REDGRAVE, Jason , HUTCHINGS, Brad , THOM, Danny
IPC分类号： G06F11/26 , G11C29/08
CPC分类号： G01R31/3177 , G06F11/221 , G11C2029/0409
摘要： Some embodiments provide an integrated circuit ("IC") with a primary circuit structure. The primary circuit structure is for performing multiple operations that implement a user design. The primary circuit structure includes multiple circuits. The IC also includes a secondary monitoring structure for monitoring multiple operations. The secondary monitoring structure includes a network communicatively coupled to multiple circuits of the primary circuit structure. The secondary monitoring circuit structure is for analyzing the monitored operations and reporting on the analysis to a circuit outside of the IC.
摘要翻译：一些实施例提供具有主电路结构的集成电路（“IC”）。主电路结构用于执行实现用户设计的多个操作。主电路结构包括多个电路。 IC还包括用于监视多个操作的二级监视结构。辅助监视结构包括通信地耦合到主电路结构的多个电路的网络。二次监视电路结构用于分析被监控的操作并将分析报告给IC外的电路。

4. 发明申请

WO2010016857A1 TRIGGER CIRCUITS AND EVENT COUNTERS FOR AN IC 审中-公开
标题翻译：触发电路和事件计数器
公开(公告)号：WO2010016857A1
公开(公告)日：2010-02-11
申请号：PCT/US2008/088492
申请日：2008-12-29
申请人： TABULA, INC. , HUTCHINGS, Brad , REDGRAVE, Jason , HUANG, Dai , TEIG, Steven
发明人： HUTCHINGS, Brad , REDGRAVE, Jason , HUANG, Dai , TEIG, Steven
IPC分类号： G06F7/38
CPC分类号： G06F1/04 , G06M3/00 , H03K19/017581 , H03K19/17728 , H03K19/17736 , H03K19/17748 , H03K19/1776 , H03K19/17764
摘要： Some embodiments provide an integrated circuit ('IC'). The IC includes multiple configurable circuits that configurably perform operations of a user design based on configuration data. The IC also includes a configurable trigger circuit that receives a set of configuration data that specifies an operational event. The configurable trigger circuit also determines whether the operational event has occurred during implementation of the user design of the IC. Additionally, the operational trigger event outputs a trigger signal upon determining that the operational trigger event has occurred.
摘要翻译：一些实施例提供集成电路（'IC'）。 IC包括可配置地基于配置数据执行用户设计操作的多个可配置电路。 IC还包括可配置触发电路，其接收指定操作事件的一组配置数据。可配置触发电路还确定在实施IC的用户设计期间是否发生了操作事件。此外，当确定操作触发事件已经发生时，操作触发事件输出触发信号。

5. 发明申请

WO2009002600A1 RESTRUCTURING DATA FROM A TRACE BUFFER OF A CONFIGURABLE IC 审中-公开
标题翻译：从可配置IC的跟踪缓冲区重新构建数据
公开(公告)号：WO2009002600A1
公开(公告)日：2008-12-31
申请号：PCT/US2008/061072
申请日：2008-04-21
申请人： TABULA, INC. , HUTCHINGS, Brad , TEIG, Steven , CALDWELL, Andrew
发明人： HUTCHINGS, Brad , TEIG, Steven , CALDWELL, Andrew
IPC分类号： G06F7/38
CPC分类号： H03K19/17752 , G06F17/5054 , H03K19/17736 , H03K19/17756 , H03K19/17764
摘要： Some embodiments provide a method that outputs from a configurable IC a first set of data bits from a trace buffer. Each bit of the first set of data bits is simultaneously generated in the configurable circuits and, in some embodiments, multiple data bits of the first set of data bits do not reach the trace buffer simultaneously. The method also determines a set of relative delays for the first set of data bits and arranges the first set of data bits into a second set of data bits by compensating for the relative delays.
摘要翻译：一些实施例提供了一种从可配置IC输出来自跟踪缓冲器的第一组数据位的方法。第一组数据位的每个位在可配置电路中同时生成，并且在一些实施例中，第一组数据位的多个数据位不会同时到达跟踪缓冲器。该方法还确定第一组数据比特的一组相对延迟，并通过补偿相对延迟将第一组数据比特排列成第二组数据比特。

6. 发明申请

WO2010033263A1 CONTROLLABLE STORAGE ELEMENTS FOR AN IC 审中-公开
标题翻译： IC的可控存储元件
公开(公告)号：WO2010033263A1
公开(公告)日：2010-03-25
申请号：PCT/US2009/033840
申请日：2009-02-11
申请人： TABULA, INC. , REDGRAVE, Jason , VOOGEL, Martin , TEIG, Steven
发明人： REDGRAVE, Jason , VOOGEL, Martin , TEIG, Steven
IPC分类号： H03K19/173
CPC分类号： H03K19/17736 , H03K19/173 , H03K19/1776
摘要： An integrated circuit ('IC') that includes a configurable routing fabric with controllable storage elements is described. The routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric may provide the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component may continually perform operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the IC.
摘要翻译：描述了包括具有可控存储元件的可配置布线结构的集成电路（'IC'）。路由结构提供了将信号路由到源节点和目的地组件之间的通信路径。路由结构可以提供选择性地将通过路由结构的信号存储在路由结构的存储元件内的能力。以这种方式，源或目的地组件可以连续地执行操作（例如，计算或路由），而不管来自或来自这样的组件的先前信号是否存储在路由结构内。源和目标组件包括可配置逻辑电路，可配置互连电路以及在整个IC中接收或分配信号的各种其他电路。

7. 发明申请

WO2009035586A1 CONFIGURATION CONTEXT SWITCHER 审中-公开
标题翻译：配置语境切换器
公开(公告)号：WO2009035586A1
公开(公告)日：2009-03-19
申请号：PCT/US2008/010526
申请日：2008-09-08
申请人： TABULA, INC. , CHANDLER, Trevis , REDGRAVE, Jason , ENTINGER, Joe , VOOGEL, Martin , TEIG, Steven
发明人： CHANDLER, Trevis , REDGRAVE, Jason , ENTINGER, Joe , VOOGEL, Martin , TEIG, Steven
IPC分类号： G11C7/00
CPC分类号： H03K19/0008 , G06F15/7867 , G11C7/1045 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H03K3/0372 , H03K19/17732 , H03K19/17748 , H03K19/17752 , H03K19/17768 , H01L2924/00 , H01L2924/00014
摘要： Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.
摘要翻译：一些实施例向IC提供配置上下文切换器。 IC包括几个可配置电路，每个可配置电路可以在任何给定时间根据当时接收到的配置数据集配置执行多个操作之一。 IC包括多个存储电路，用于存储每个可配置电路的几个配置数据组。 IC还包括用于将可配置电路可切换地连接到不同组的存储电路以接收不同组的配置数据集的上下文切换互连电路。上下文切换器包括用于重新定时来自配置存储元件的数据的一个或多个阶段。这些阶段可以包括互连电路或存储电路。一些实施例构建配置数据存储元件中的一个阶段。一些实施例对配置数据位进行编码，并因此利用上下文切换器中的解码器对编码的配置数据进行解码。

8. 发明申请

WO2011162858A1 RESCALING 审中-公开
标题翻译：重新缩放
公开(公告)号：WO2011162858A1
公开(公告)日：2011-12-29
申请号：PCT/US2011/031482
申请日：2011-04-06
申请人： TABULA, INC. , WEBER, Scott, J. , EBELING, Christopher, D. , CALDWELL, Andrew , TEIG, Steven , CALLAHAN, Timothy, J. , NGUYEN, Hung, Q. , SUN, Shangzhi , YEOLE, Shilpa, V.
发明人： WEBER, Scott, J. , EBELING, Christopher, D. , CALDWELL, Andrew , TEIG, Steven , CALLAHAN, Timothy, J. , NGUYEN, Hung, Q. , SUN, Shangzhi , YEOLE, Shilpa, V.
IPC分类号： H03K19/173
CPC分类号： G06F17/5077 , G06F17/5045 , G06F17/505 , G06F17/5054
摘要： A novel method for designing an integrated circuit ("IC") by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.
摘要翻译：公开了一种通过在IC的设计中重新调整原始电路组来设计集成电路（“IC”）的新颖方法。要重新缩放的原始电路组包括顺序节点，组合节点和互连。每个顺序节点与时钟的相位相关联。该方法产生包括电路的多个复制集合的重新定标的电路集合。每个电路副本集合包括与原始电路组中的节点和互连相同的顺序节点，组合节点和互连。每个顺序节点与时钟的相位相关联，时钟的相位是原始集合中其对应的顺序元素的相位的一小部分。该方法将每个电路副本中的节点连接到另一副本集中的逻辑等效节点。该方法用重新定标的电路组替换原始电路组。

9. 发明申请

WO2011123151A1 SYSTEM AND METHOD FOR REDUCING RECONFIGURATION POWER USAGE 审中-公开
标题翻译：减少重新配置电力使用的系统和方法
公开(公告)号：WO2011123151A1
公开(公告)日：2011-10-06
申请号：PCT/US2010/053487
申请日：2010-10-21
申请人： TABULA INC. , HUANG, Randy, R. , VOOGEL, Martin , HU, Jingcao , TEIG, Steven
发明人： HUANG, Randy, R. , VOOGEL, Martin , HU, Jingcao , TEIG, Steven
IPC分类号： H03K19/173
CPC分类号： H03K19/0008 , G06F17/50 , G06F17/5054 , G06F17/5072 , G06F17/5077 , G06F17/5081 , G06F2217/78 , H03K19/1737 , H03K19/17748 , H03K19/17756 , H03K19/17784 , H03K19/17796
摘要： A system and method for reducing power consumption in a reconfigurable integrated circuit. Some embodiments provide placement and routing programs that reduce the number of bits to be reconfigured. Some embodiments provide placement and routing programs that increase the number of groups of circuits that do not need reconfiguration at some times. Some embodiments include circuits that selectively block reconfiguration.
摘要翻译：一种用于降低可重构集成电路中的功耗的系统和方法。一些实施例提供了减少要重新配置的比特数的布局和路由程序。一些实施例提供了放置和路由程序，其增加了在某些时间不需要重新配置的电路组的数量。一些实施例包括选择性地阻止重新配置的电路。

10. 发明申请

WO2009151934A1 DECISION MODULES 审中-公开
标题翻译：决策模块
公开(公告)号：WO2009151934A1
公开(公告)日：2009-12-17
申请号：PCT/US2009/045096
申请日：2009-05-22
申请人： TABULA, INC. , CALDWELL, Andrew , TEIG, Steven
发明人： CALDWELL, Andrew , TEIG, Steven
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/505 , G06F17/5072 , G06F17/5077 , G06F17/5081
摘要： An abstract decision module primitive for placement within a logical representation ( i.e ., a netlist) of a circuit design is described. The decision module primitive receives as inputs alternative solutions for a given function or segment of a netlist. The alternative solutions include functionally equivalent, but structurally different implementations of the function or segment of the netlist. The decision module primitive alternatively selects between connecting one of the inputs to the netlist to provide a complete functional definition for the netlist based on constraint information. The selected input of the decision module may be updated as additional constraint information is determined throughout the various stages of the design process. In addition, alternative solutions for a given function or segment of the netlist may be added to and/or removed from the inputs of a decision module as additional constraint information is identified.
摘要翻译：描述了用于放置在电路设计的逻辑表示（即，网表中）的抽象决策模块原语。决策模块原语接收网表的给定功能或段的输入替代解决方案。替代解决方案包括功能等同，但在网表的功能或段的结构上不同的实现。所述决策模块基元可选择在连接到所述网表之一的输入之间，以基于约束信息为所述网表提供完整的功能定义。当在设计过程的各个阶段确定附加约束信息时，可以更新决策模块的所选择的输入。此外，当识别出额外的约束信息时，可以向决策模块的输入添加和/或从其中删除网表的给定功能或段的替代解决方案。

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