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1. 发明授权

US09501597B2 Elimination of illegal states within equivalence checking 有权
标题翻译：在等值检查中消除非法国家
公开(公告)号：US09501597B2
公开(公告)日：2016-11-22
申请号：US14329494
申请日：2014-07-11
申请人： Synopsys, Inc.
发明人： Himanshu Jain , Carl Preston Pixley
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5045 , G06F17/504 , G06F17/5081
摘要： A method for equivalence checking includes obtaining a first and a second representation for a semiconductor design and applying a set of inputs to both representations. The outputs of the first representation are compared to the outputs of the second representation. If a mismatch is found, the starting states for the first and second representations are evaluated using a model checker to see if they are reachable from a known legal state such as reset state for that representation. If both of the starting states are reachable, the mismatch is a real mismatch providing a counter-example of the equivalence of the two representations. If one or both of the starting states are unreachable, the mismatch is a spurious mismatch and the model checker can be used to generate an invariant to preclude those starting states in future iterations of the equivalence checker.
摘要翻译：一种用于等效性检查的方法包括获得用于半导体设计的第一和第二表示以及将一组输入应用于两个表示。将第一表示的输出与第二表示的输出进行比较。如果发现不匹配，则使用模型检查器来评估第一和第二表示的起始状态，以查看它们是否可以从已知的合法状态（例如该表示的复位状态）到达。如果两个起始状态都可达到，则不匹配是提供两个表示的等价性的反例的实际失配。如果一个或两个起始状态是不可达的，则不匹配是虚假失配，并且可以使用模型检验器来生成不变量以排除等同检查器的将来迭代中的那些起始状态。

2. 发明申请

US20160012167A1 ELIMINATION OF ILLEGAL STATES WITHIN EQUIVALENCE CHECKING 有权
标题翻译：在等效检查中消除非法国家
公开(公告)号：US20160012167A1
公开(公告)日：2016-01-14
申请号：US14329494
申请日：2014-07-11
申请人： Synopsys, Inc.
发明人： Himanshu Jain , Carl Preston Pixley
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/504 , G06F17/5081
摘要： A method for equivalence checking includes obtaining a first and a second representation for a semiconductor design and applying a set of inputs to both representations. The outputs of the first representation are compared to the outputs of the second representation. If a mismatch is found, the starting states for the first and second representations are evaluated using a model checker to see if they are reachable from a known legal state such as reset state for that representation. If both of the starting states are reachable, the mismatch is a real mismatch providing a counter-example of the equivalence of the two representations. If one or both of the starting states are unreachable, the mismatch is a spurious mismatch and the model checker can be used to generate an invariant to preclude those starting states in future iterations of the equivalence checker.
摘要翻译：一种用于等效性检查的方法包括获得用于半导体设计的第一和第二表示以及将一组输入应用于两个表示。将第一表示的输出与第二表示的输出进行比较。如果发现不匹配，则使用模型检查器来评估第一和第二表示的起始状态，以查看它们是否可以从已知的合法状态（例如该表示的复位状态）到达。如果两个起始状态都可达到，则不匹配是提供两个表示的等价性的反例的实际失配。如果一个或两个起始状态是不可达的，则不匹配是虚假失配，并且可以使用模型检验器来生成不变量以排除等同检查器的将来迭代中的那些起始状态。

3. 发明授权

US08914758B1 Equivalence checking using structural analysis on data flow graphs 有权
标题翻译：对数据流图进行结构分析的等效性检查
公开(公告)号：US08914758B1
公开(公告)日：2014-12-16
申请号：US13903967
申请日：2013-05-28
申请人： Synopsys, Inc.
发明人： Sudipta Kundu , Carl Preston Pixley
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5036
摘要： A design is verified by using equivalence checking to compare a word-level description of the design to a bit-level description of the design. A word-level data flow graph (DFG) based on the word-level description and a bit-level DFG is obtained. Structural analysis is used to reduce the graphs and partition them into smaller portions for the equivalence checking. The analysis includes searching the bit-level DFG to find partial-product encoding and removing redundancy from the bit-level DFG. A reference model with architectural information from the bit-level DFG is created based on the word-level DFG. The reference model is reduced and equivalence checked against the bit-level DFG to determine if the word-level description is equivalent to the bit-level description.
摘要翻译：通过使用等价性检查来验证设计，以将设计的字级描述与设计的位级描述进行比较。获得基于字级描述和位级DFG的字级数据流图（DFG）。结构分析用于减少图形并将其分割成更小的部分进行等价性检查。分析包括搜索位级DFG以寻找部分产品编码并从位级DFG中去除冗余。基于字级DFG创建了具有来自位级DFG的架构信息的参考模型。参考模型被减少并且与位级DFG进行等价性检查，以确定字级描述是否等同于位级描述。

4. 发明申请

US20140359545A1 EQUIVALENCE CHECKING USING STRUCTURAL ANALYSIS ON DATA FLOW GRAPHS 有权
标题翻译：使用结构分析数据流图进行等效检查
公开(公告)号：US20140359545A1
公开(公告)日：2014-12-04
申请号：US13903967
申请日：2013-05-28
申请人： Synopsys, Inc
发明人： Sudipta Kundu , Carl Preston Pixley
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A design is verified by using equivalence checking to compare a word-level description of the design to a bit-level description of the design. A word-level data flow graph (DFG) based on the word-level description and a bit-level DFG is obtained. Structural analysis is used to reduce the graphs and partition them into smaller portions for the equivalence checking. The analysis includes searching the bit-level DFG to find partial-product encoding and removing redundancy from the bit-level DFG. A reference model with architectural information from the bit-level DFG is created based on the word-level DFG. The reference model is reduced and equivalence checked against the bit-level DFG to determine if the word-level description is equivalent to the bit-level description.
摘要翻译：通过使用等价性检查来验证设计，以将设计的字级描述与设计的位级描述进行比较。获得基于字级描述和位级DFG的字级数据流图（DFG）。结构分析用于减少图形并将其分割成更小的部分进行等价性检查。分析包括搜索位级DFG以寻找部分产品编码并从位级DFG中去除冗余。基于字级DFG创建了具有来自位级DFG的架构信息的参考模型。参考模型被减少并且与位级DFG进行等价性检查，以确定字级描述是否等同于位级描述。

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