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1. 发明授权

US08329549B2 Enhancing integrity of a high-k gate stack by protecting a liner at the gate bottom during gate head exposure 失效
标题翻译：通过在栅极头暴露期间保护栅极底部的衬垫，提高高k栅极堆叠的完整性
公开(公告)号：US08329549B2
公开(公告)日：2012-12-11
申请号：US12624672
申请日：2009-11-24
申请人： Sven Beyer , Frank Seliger , Gunter Grasshoff
发明人： Sven Beyer , Frank Seliger , Gunter Grasshoff
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/28123 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/4966 , H01L29/517 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7848
摘要： Sophisticated gate stacks including a high-k dielectric material and a metal-containing electrode material may be covered by a protection liner, such as a silicon nitride liner, which may be maintained throughout the entire manufacturing sequence at the bottom of the gate stacks. For this purpose, a mask material may be applied prior to removing cap materials and spacer layers that may be used for encapsulating the gate stacks during the selective epitaxial growth of a strain-inducing semiconductor alloy. Consequently, enhanced integrity may be maintained throughout the entire manufacturing sequence, while at the same time one or more lithography processes may be avoided.
摘要翻译：包括高k电介质材料和含金属的电极材料的复杂的栅极堆叠可以被诸如氮化硅衬垫的保护衬垫覆盖，其可以在栅堆叠的底部的整个制造顺序中保持。为了这个目的，可以在除去在应变诱导半导体合金的选择性外延生长期间可用于封装栅极叠层的覆盖材料和间隔层之前施加掩模材料。因此，可以在整个制造顺序中保持增强的完整性，同时可以避免一个或多个光刻工艺。

2. 发明申请

US20100136762A1 ENHANCING INTEGRITY OF A HIGH-K GATE STACK BY PROTECTING A LINER AT THE GATE BOTTOM DURING GATE HEAD EXPOSURE 失效
标题翻译：通过在门头暴露期间保护门底部的门锁提高高K门架的完整性
公开(公告)号：US20100136762A1
公开(公告)日：2010-06-03
申请号：US12624672
申请日：2009-11-24
申请人： Sven Beyer , Frank Seliger , Gunter Grasshoff
发明人： Sven Beyer , Frank Seliger , Gunter Grasshoff
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/28123 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/4966 , H01L29/517 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7848
摘要： Sophisticated gate stacks including a high-k dielectric material and a metal-containing electrode material may be covered by a protection liner, such as a silicon nitride liner, which may be maintained throughout the entire manufacturing sequence at the bottom of the gate stacks. For this purpose, a mask material may be applied prior to removing cap materials and spacer layers that may be used for encapsulating the gate stacks during the selective epitaxial growth of a strain-inducing semiconductor alloy. Consequently, enhanced integrity may be maintained throughout the entire manufacturing sequence, while at the same time one or more lithography processes may be avoided.
摘要翻译：包括高k电介质材料和含金属的电极材料的复杂的栅极堆叠可以被诸如氮化硅衬垫的保护衬垫覆盖，其可以在栅堆叠的底部的整个制造顺序中保持。为了这个目的，可以在除去在应变诱导半导体合金的选择性外延生长期间可用于封装栅极叠层的覆盖材料和间隔层之前施加掩模材料。因此，可以在整个制造顺序中保持增强的完整性，同时可以避免一个或多个光刻工艺。

3. 发明申请

US20100025742A1 TRANSISTOR HAVING A STRAINED CHANNEL REGION CAUSED BY HYDROGEN-INDUCED LATTICE DEFORMATION 审中-公开
标题翻译：由氢诱导的层状变形引起的应变通道区域的晶体管
公开(公告)号：US20100025742A1
公开(公告)日：2010-02-04
申请号：US12476376
申请日：2009-06-02
申请人： Sven Beyer , Andreas Hellmich , Gunter Grasshoff , Hans-Juergen Engelmann
发明人： Sven Beyer , Andreas Hellmich , Gunter Grasshoff , Hans-Juergen Engelmann
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/2652 , H01L21/263 , H01L21/26506 , H01L29/6659 , H01L29/7833 , H01L29/7842
摘要： A lattice distortion may be achieved by incorporating a hydrogen species into a semiconductor material, such as silicon, without destroying the lattice structure. For example, by incorporating the hydrogen species on the basis of an electron shower, a tensile strain component may be obtained in the channel of N-channel transistors.
摘要翻译：可以通过将氢物质引入半导体材料（例如硅）中而不破坏晶格结构来实现晶格畸变。例如，通过在电子淋浴的基础上并入氢物质，可以在N沟道晶体管的沟道中获得拉伸应变分量。

4. 发明申请

US20130109174A1 Methods of Forming Conductive Structures Using a Spacer Erosion Technique 有权
标题翻译：使用间隔侵蚀技术形成导电结构的方法
公开(公告)号：US20130109174A1
公开(公告)日：2013-05-02
申请号：US13281552
申请日：2011-10-26
申请人： Gunter Grasshoff
发明人： Gunter Grasshoff
IPC分类号： H01L21/768 , H01L21/302
CPC分类号： H01L21/76811 , H01L21/31144 , H01L2221/1063
摘要： Disclosed herein are various methods of forming conductive structures, such as conductive lines and via, on an integrated circuit device using a spacer erosion technique. In one example, the method includes forming a patterned hard mask layer above a layer of insulating material, the patterned hard mask having a hard mask opening, forming an erodible spacer in the hard mask opening to thereby define a spacer opening and performing at least one etching process through the spacer opening on the layer of insulating material to define a trench therein for a conductive structure, wherein the erodible spacer is substantially eroded away during the at least one etching process.
摘要翻译：这里公开了在使用间隔物侵蚀技术的集成电路装置上形成诸如导电线和通孔的导电结构的各种方法。在一个示例中，该方法包括在绝缘材料层之上形成图案化的硬掩模层，图案化的硬掩模具有硬掩模开口，在硬掩模开口中形成可蚀刻间隔物，从而限定间隔开口并执行至少一个通过绝缘材料层上的间隔开口蚀刻工艺，以在其中限定用于导电结构的沟槽，其中在至少一个蚀刻工艺期间，可蚀刻间隔物基本上被腐蚀掉。

5. 发明授权

US07723174B2 CMOS device comprising MOS transistors with recessed drain and source areas and a SI/GE material in the drain and source areas of the PMOS transistor 有权
标题翻译： CMOS器件包括具有凹陷漏极和源极区的MOS晶体管和PMOS晶体管的漏极和源极区中的SI / GE材料
公开(公告)号：US07723174B2
公开(公告)日：2010-05-25
申请号：US12464161
申请日：2009-05-12
申请人： Andrew Waite , Andy Wei , Gunter Grasshoff
发明人： Andrew Waite , Andy Wei , Gunter Grasshoff
IPC分类号： H01L21/76 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L29/665 , H01L29/66545 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： The present disclosure relates to semiconductor devices and a process sequence in which a semiconductor alloy, such as silicon/germanium, may be formed in an early manufacturing stage, wherein other performance-increasing mechanisms, such as a recessed drain and source configuration, possibly in combination with high-k dielectrics and metal gates, may be incorporated in an efficient manner while still maintaining a high degree of compatibility with conventional process techniques.
摘要翻译：本公开涉及半导体器件和其中可以在早期制造阶段中形成诸如硅/锗的半导体合金的工艺顺序，其中其它性能增加机制，例如凹陷漏极和源极配置，可能在与高k电介质和金属栅极的组合可以以有效的方式并入，同时仍然保持与常规工艺技术的高度兼容性。

6. 发明授权

US07381622B2 Method for forming embedded strained drain/source regions based on a combined spacer and cavity etch process 有权
标题翻译：基于组合间隔件和腔蚀刻工艺形成嵌入式应变漏极/源极区域的方法
公开(公告)号：US07381622B2
公开(公告)日：2008-06-03
申请号：US11559462
申请日：2006-11-14
申请人： Andreas Hellmich , Gunter Grasshoff , Fernando Koch , Andy Wei , Thorsten Kammler
发明人： Andreas Hellmich , Gunter Grasshoff , Fernando Koch , Andy Wei , Thorsten Kammler
IPC分类号： H01L21/338 , H01L21/8238 , H01L21/336 , H01L21/461 , H01L21/302
CPC分类号： H01L29/66628 , H01L21/31116 , H01L21/31138 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/165 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66636 , H01L29/7848
摘要： By patterning a spacer layer stack and etching a cavity in an in situ etch process, the process complexity, as well as the uniformity, during the formation of embedded strained semiconductor layers may be significantly enhanced. In an initial phase, the spacer layer stack may be patterned on the basis of an anisotropic etch step with a high degree of uniformity, since a selectivity between individual stack layers may not be necessary. Thereafter, a cleaning process may be performed followed by a cavity etch process, wherein a reduced over-etch time during the spacer patterning process significantly contributes to the uniformity of the finally obtained cavities, while the in situ nature of the process also provides a reduced overall process time.
摘要翻译：通过图案化间隔层堆叠并在原位蚀刻工艺中蚀刻空腔，可以显着增强在嵌入的应变半导体层的形成期间的工艺复杂性以及均匀性。在初始阶段中，间隔层堆叠可以在具有高度均匀性的各向异性蚀刻步骤的基础上进行图案化，因为可能不需要各个层叠层之间的选择性。此后，可以进行清洁处理，然后进行腔蚀刻工艺，其中在间隔物图案化过程期间减少的过度蚀刻时间显着有助于最终获得的空腔的均匀性，而工艺的原位性质也提供了减少的整个处理时间。

7. 发明申请

US20070232006A1 METHOD FOR FORMING EMBEDDED STRAINED DRAIN/SOURCE REGIONS BASED ON A COMBINED SPACER AND CAVITY ETCH PROCESS 有权
标题翻译：基于组合间隔和孔蚀刻过程形成嵌入式应变排水/源区的方法
公开(公告)号：US20070232006A1
公开(公告)日：2007-10-04
申请号：US11559462
申请日：2006-11-14
申请人： Andreas Hellmich , Gunter Grasshoff , Fernando Koch , Andy Wei , Thorsten Kammler
发明人： Andreas Hellmich , Gunter Grasshoff , Fernando Koch , Andy Wei , Thorsten Kammler
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L21/31116 , H01L21/31138 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/165 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66636 , H01L29/7848
摘要： By patterning a spacer layer stack and etching a cavity in an in situ etch process, the process complexity, as well as the uniformity, during the formation of embedded strained semiconductor layers may be significantly enhanced. In an initial phase, the spacer layer stack may be patterned on the basis of an anisotropic etch step with a high degree of uniformity, since a selectivity between individual stack layers may not be necessary. Thereafter, a cleaning process may be performed followed by a cavity etch process, wherein a reduced over-etch time during the spacer patterning process significantly contributes to the uniformity of the finally obtained cavities, while the in situ nature of the process also provides a reduced overall process time.
摘要翻译：通过图案化间隔层堆叠并在原位蚀刻工艺中蚀刻空腔，可以显着增强在嵌入的应变半导体层的形成期间的工艺复杂性以及均匀性。在初始阶段中，间隔层堆叠可以在具有高度均匀性的各向异性蚀刻步骤的基础上进行图案化，因为可能不需要各个层叠层之间的选择性。此后，可以进行清洁处理，然后进行腔蚀刻工艺，其中在间隔物图案化过程期间减少的过度蚀刻时间显着有助于最终获得的空腔的均匀性，而工艺的原位性质也提供了减少的整个处理时间。

8. 发明授权

US08791017B2 Methods of forming conductive structures using a spacer erosion technique 有权
标题翻译：使用间隔侵蚀技术形成导电结构的方法
公开(公告)号：US08791017B2
公开(公告)日：2014-07-29
申请号：US13281552
申请日：2011-10-26
申请人： Gunter Grasshoff
发明人： Gunter Grasshoff
IPC分类号： H01L21/768 , H01L21/302
CPC分类号： H01L21/76811 , H01L21/31144 , H01L2221/1063
摘要： Disclosed herein are various methods of forming conductive structures, such as conductive lines and via, on an integrated circuit device using a spacer erosion technique. In one example, the method includes forming a patterned hard mask layer above a layer of insulating material, the patterned hard mask having a hard mask opening, forming an erodible spacer in the hard mask opening to thereby define a spacer opening and performing at least one etching process through the spacer opening on the layer of insulating material to define a trench therein for a conductive structure, wherein the erodible spacer is substantially eroded away during the at least one etching process.
摘要翻译：这里公开了在使用间隔物侵蚀技术的集成电路装置上形成诸如导电线和通孔的导电结构的各种方法。在一个示例中，该方法包括在绝缘材料层之上形成图案化的硬掩模层，图案化的硬掩模具有硬掩模开口，在硬掩模开口中形成可蚀刻间隔物，从而限定间隔开口并执行至少一个通过绝缘材料层上的间隔开口蚀刻工艺，以在其中限定用于导电结构的沟槽，其中在至少一个蚀刻工艺期间，可蚀刻间隔物基本上被腐蚀掉。

9. 发明授权

US08021942B2 Method of forming CMOS device having gate insulation layers of different type and thickness 有权
标题翻译：形成具有不同类型和厚度的栅极绝缘层的CMOS器件的方法
公开(公告)号：US08021942B2
公开(公告)日：2011-09-20
申请号：US12049548
申请日：2008-03-17
申请人： Andy Wei , Andrew Waite , Martin Trentzsch , Johannes Groschopf , Gunter Grasshoff , Andreas Ott
发明人： Andy Wei , Andrew Waite , Martin Trentzsch , Johannes Groschopf , Gunter Grasshoff , Andreas Ott
IPC分类号： H01L21/8238 , H01L21/70 , H01L27/092
CPC分类号： H01L21/82345 , H01L21/823462 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/84 , H01L27/088 , H01L27/0922 , H01L29/66545 , H01L29/7843 , H01L29/7848 , Y10S438/926
摘要： In the process sequence for replacing conventional gate electrode structures by high-k metal gate structures, the number of additional masking steps may be maintained at a low level, for instance by using highly selective etch steps, thereby maintaining a high degree of compatibility with conventional CMOS techniques. Furthermore, the techniques disclosed herein enable compatibility to front-end process techniques and back-end process techniques, thereby allowing the integration of well-established strain-inducing mechanisms in the transistor level as well as in the contact level.
摘要翻译：在通过高k金属栅极结构代替常规栅电极结构的工艺顺序中，例如通过使用高选择性蚀刻步骤，附加掩模步骤的数量可以保持在低水平，从而保持与常规栅极结构的高度兼容性 CMOS技术。此外，本文公开的技术使得能够与前端处理技术和后端处理技术兼容，从而允许将已建立的应变诱发机制集成在晶体管级以及接触级中。

10. 发明授权

US06875676B2 Methods for producing a highly doped electrode for a field effect transistor 失效
标题翻译：用于产生用于场效应晶体管的高掺杂电极的方法
公开(公告)号：US06875676B2
公开(公告)日：2005-04-05
申请号：US10359980
申请日：2003-02-06
申请人： Karsten Wieczorek , Falk Graetsch , Gunter Grasshoff
发明人： Karsten Wieczorek , Falk Graetsch , Gunter Grasshoff
IPC分类号： H01L21/28 , H01L21/3215 , H01L29/49 , H01L21/20
CPC分类号： H01L21/28035 , H01L21/32155 , H01L29/4925
摘要： A highly localized diffusion barrier is incorporated into a polysilicon line to allow the doping of the polysilicon layer without sacrificing an underlying material layer. The diffusion barrier is formed by depositing a thin polysilicon layer and exposing the layer to a nitrogen-containing plasma ambient. Thereafter, the deposition is resumed to obtain the required final thickness. Moreover, a polysilicon line is disclosed, having a highly localized barrier layer.
摘要翻译：高度局部化的扩散势垒被并入到多晶硅线中以允许多晶硅层的掺杂而不牺牲下面的材料层。通过沉积薄的多晶硅层并将该层暴露于含氮等离子体环境中而形成扩散阻挡层。此后，恢复沉积以获得所需的最终厚度。此外，公开了具有高度局部化的阻挡层的多晶硅线。

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