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1. 发明授权

US07120686B2 Method and system for notification of maintenance information using portable terminal and computer program product 失效
标题翻译：使用便携式终端和计算机程序产品通知维护信息的方法和系统
公开(公告)号：US07120686B2
公开(公告)日：2006-10-10
申请号：US09906136
申请日：2001-07-17
申请人： Susumu Sasabe , Shin-Ichiro Hayano , Toshibumi Kawano , Yasuhiro Uemura , Hiroyuki Hayashi , Shingo Fukui
发明人： Susumu Sasabe , Shin-Ichiro Hayano , Toshibumi Kawano , Yasuhiro Uemura , Hiroyuki Hayashi , Shingo Fukui
IPC分类号： G06F15/173
CPC分类号： H04L41/026 , H04L41/0253 , H04L41/06 , H04L41/18
摘要： A maintenance information providing server (Web server) 20 that transmits maintenance information to a portable terminal carried by a vendor or a customer is appended to the network management system (NMS) 21 supervising the network 2, server 20 on receipt of malfunction information from the NMS 21, notifying the malfunction to one or more pre-registered portable terminals (23, 13, 33) of a communication service purveyor, vendor or the customer.
摘要翻译：将维护信息提供服务器（Web服务器）20发送到由供应商或客户携带的便携式终端的维护信息提供服务器（20）附加到网络管理系统（NMS）21，网络管理系统（NMS）21在接收到来自 NMS 21向通信服务提供商，供应商或客户的一个或多个预先注册的便携式终端（23,13,33）通知故障。

2. 发明授权

US4701817A Loading and ejecting mechanism for a magnetic tape cassette apparatus 失效
标题翻译：磁带盒装置的装载和排出机构
公开(公告)号：US4701817A
公开(公告)日：1987-10-20
申请号：US658293
申请日：1984-10-05
申请人： Yasuhiro Uemura
发明人： Yasuhiro Uemura
IPC分类号： G11B15/07 , G11B15/30 , G11B15/675 , G11B5/008 , G11B15/00
CPC分类号： G11B15/67513
摘要： An apparatus suitable for digital data transfer with a tape cassette is designed to require no movement of a magnetic transducer head to establish data transfer contact between the head and a tape cassette. The tape cassette is inserted in the apparatus in the direction of a notional line intersecting at right angles the axes of rotation of the pair of hubs of the tape cassette. Upon full insertion in the apparatus the tape cassette has its apertured front side held opposite the transducer head. A cassette shift mechanism subsequently transports the loaded tape cassette in a direction normal to the notional line, into data transfer contact with the transducer head. A tape transport shift mechanism also operates to move a pair of motor driven spindles into driving engagement with the respective hubs of the tape cassette. The insertion of the tape cassette automatically triggers the operation of both cassette shift mechanism and tape transport shift mechanism. A preferred embodiment additionally comprises an ejector mechanism including a pushbutton. Upon activation of this ejector pushbutton the tape transport shift mechanism moves the drive spindles out of engagement with the cassette hubs, and the cassette shift mechanism retracts the cassette away from the transducer head and further ejects the cassette from the apparatus.
摘要翻译：适用于带盒的数字数据传输的装置被设计成不需要磁性传感器头的移动，以在磁头和磁带盒之间建立数据传送接触。磁带盒沿着与磁带盒的一对轮毂的旋转轴线成直角相交的概念线的方向插入设备中。当磁带盒完全插入设备中时，磁带盒的开孔前侧保持与换能器头相对。盒式换档机构随后将装载的盒式磁带沿垂直于图形线的方向传送到与换能器头部的数据传送接触。磁带传送换档机构还操作以将一对电动机驱动的主轴移动成与磁带盒的各个毂的驱动接合。磁带盒的插入自动触发盒式换档机构和磁带传送换档机构的操作。优选实施例还包括包括按钮的喷射器机构。在启动该喷射器按钮时，带传送换档机构将驱动主轴移动离开与盒毂的接合，并且盒的换档机构使盒远离换能器头退回并进一步从装置中弹出盒。

3. 发明授权

US6069793A Circuit module and information processing apparatus 失效
标题翻译：电路模块及信息处理装置
公开(公告)号：US6069793A
公开(公告)日：2000-05-30
申请号：US10185
申请日：1998-01-21
申请人： Takashi Maruyama , Akira Yamagiwa , Ryoichi Kurihara , Masakazu Sakaue , Yasuhiro Uemura , Mikihiro Tanaka
发明人： Takashi Maruyama , Akira Yamagiwa , Ryoichi Kurihara , Masakazu Sakaue , Yasuhiro Uemura , Mikihiro Tanaka
IPC分类号： G06F1/20 , H01L23/36 , H05K7/20
CPC分类号： G06F1/206 , G06F1/20 , G06F1/203 , H01L23/36 , H01L2224/05599 , H01L2224/16225 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2224/85399 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2924/00014 , H01L2924/01079 , H01L2924/10253 , H01L2924/15311 , H01L2924/19105 , H01L2924/3025
摘要： The present invention provides an information processing apparatus that may be designed in small and thin size and a small and thin CPU module that has a nigh heat releasing effect and is suitable therefor. The CPU module includes a processor, a connector to be electrically connected to the outside, a system control circuit for controlling transfer of a signal between the processor and the connector, and a printed board on which the processor, the connector and the system control circuit are mounted. The CPU module further provides a heat release plate one side of which is pasted with the printed board and the other side of which is substantially planar. The printed board has a cavity formed therein so that the processor may be fitted in the cavity in a bare-chip state. One side of the bare chip is jointed with the heat release plate.
摘要翻译：本发明提供一种可以设计成小型和小型的信息处理设备，以及具有最佳散热效果并且适合的小型和薄型CPU模块。 CPU模块包括处理器，电连接到外部的连接器，用于控制处理器和连接器之间的信号传送的系统控制电路，以及印刷电路板，处理器，连接器和系统控制电路被安装。 CPU模块还提供一个散热片，其一面与印刷电路板粘贴，另一侧基本上是平面的。印刷板具有形成在其中的空腔，使得处理器可以以裸芯片状态装配在空腔中。裸芯片的一侧与散热板接合。

4. 发明授权

US06829574B1 Logic emulation module and logic emulation board 有权
标题翻译：逻辑仿真模块和逻辑仿真板
公开(公告)号：US06829574B1
公开(公告)日：2004-12-07
申请号：US09328800
申请日：1999-06-09
申请人： Hiroshi Ito , Akira Yamagiwa , Nobuaki Ejima , Ryoichi Kurihara , Masakazu Sakaue , Yasuhiro Uemura
发明人： Hiroshi Ito , Akira Yamagiwa , Nobuaki Ejima , Ryoichi Kurihara , Masakazu Sakaue , Yasuhiro Uemura
IPC分类号： G06F9455
CPC分类号： G06F17/5027 , H01L2224/16 , H01L2924/13091 , H01L2924/00
摘要： Disclosed herein is an improved logic module used for logic emulation along with an enhanced logic emulation board subject to logic verification. The logic module has a plurality of programmable LSIs capable of programming logic and a plurality of switching LSIs capable of programming connections, the LSIs being mounted on one or both sides of a board. Peripheral portions of the board carry connectors for electrical connection to the outside. There are two types of data lines: those directly coupling the connectors to the programmable LSIs, and those linking the connectors to the programmable LSIs via the switching LSIs. The programmable and switching LSIs constitute a crossbar connection arrangement. The logic emulation board has connectors for connection to a logic emulation module, and lands for supporting LSIs targeted for development. Pins of the connectors and the lands are interconnected on a one-to-one basis. Also disclosed here is an upgraded module structure permitting a multiple-stage module setup together with an advanced cooling structure for modules.
摘要翻译：这里公开了一种用于逻辑仿真的改进的逻辑模块以及经过逻辑验证的增强型逻辑仿真板。逻辑模块具有能够编程逻辑的多个可编程LSI和能够编程连接的多个开关LSI，LSI安装在板的一侧或两侧。板的外围部分携带用于与外部电连接的连接器。有两种类型的数据线：将连接器直接耦合到可编程LSI的数据线，以及通过开关LSI将连接器连接到可编程LSI的那些。可编程和开关式LSI构成了一种交叉连接装置。逻辑仿真板具有用于连接到逻辑仿真模块的连接器，并且用于支持用于开发的LSI的接地。连接器和焊盘的引脚是以一对一的方式相互连接的。这里还公开了一种升级的模块结构，允许多级模块与模块的先进冷却结构一起设置。

5. 发明授权

US06266242B1 Circuit module and information processing apparatus 有权
标题翻译：电路模块及信息处理装置
公开(公告)号：US06266242B1
公开(公告)日：2001-07-24
申请号：US09557161
申请日：2000-04-25
申请人： Takashi Maruyama , Akira Yamagiwa , Ryoichi Kurihara , Masakazu Sakaue , Yasuhiro Uemura , Mikihiro Tanaka
发明人： Takashi Maruyama , Akira Yamagiwa , Ryoichi Kurihara , Masakazu Sakaue , Yasuhiro Uemura , Mikihiro Tanaka
IPC分类号： H05K720
CPC分类号： G06F1/206 , G06F1/20 , G06F1/203 , H01L23/36 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/05599 , H01L2224/16225 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01079 , H01L2924/10253 , H01L2924/15311 , H01L2924/19105 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： The present invention provides an information processing apparatus that may be designed in small and thin size and a small and thin CPU module that has a high heat releasing effect and is suitable therefor. The CPU module includes a processor, a connector to be electrically connected to the outside, a system control circuit for controlling transfer of a signal between the processor and the connector, and a printed board on which the processor, the connector and the system control circuit are mounted. The CPU module further provides a heat release plate one side of which is pasted with the printed board and the other side of which is substantially planar. The printed board has a cavity formed therein so that the processor may be fitted in the cavity in a bare-chip state. One side of the bare chip is jointed with the heat release plate.
摘要翻译：本发明提供一种信息处理装置，其可以设计成小而薄的小型和薄型CPU模块，其具有高的散热效果并且适合于此。 CPU模块包括处理器，电连接到外部的连接器，用于控制处理器和连接器之间的信号传送的系统控制电路，以及印刷电路板，处理器，连接器和系统控制电路被安装。 CPU模块还提供一个散热片，其一面与印刷电路板粘贴，另一侧基本上是平面的。印刷板具有形成在其中的空腔，使得处理器可以以裸芯片状态装配在空腔中。裸芯片的一侧与散热板接合。

6. 发明授权

US07580443B2 Clock generating method and clock generating circuit 失效
标题翻译：时钟产生方法和时钟发生电路
公开(公告)号：US07580443B2
公开(公告)日：2009-08-25
申请号：US11331154
申请日：2006-01-13
申请人： Yasuhiro Uemura , Takashi Nakamura , Akio Katsushima , Makoto Funatsu
发明人： Yasuhiro Uemura , Takashi Nakamura , Akio Katsushima , Makoto Funatsu
IPC分类号： H04B1/69
CPC分类号： H04B15/02 , H03C3/0925 , H03C3/0933 , H04B2215/067
摘要： In a clock generating circuit, while a PLL (Phase-Locked Loop) circuit and a modulator are employed, when a frequency dividing ratio of a feedback-purpose frequency divider in the PLL circuit is changed in accordance with modulation data produced based upon a modulation profile of the modulator to perform a frequency modulation so as to spread a spectrum, a turning point of the modulation profile is moved so as to disperse a degree of frequency, so that the spread spectrum is re-spread. Also, a clock generating circuit is constituted by a PLL circuit and a modulator, a multiple modulation profile generating circuit is provided in the modulator, and a turning point of a modulation profile is moved so as to disperse a degree of frequency, so that a spread spectrum is re-spread.
摘要翻译：在时钟发生电路中，当使用PLL（锁相环）电路和调制器时，当PLL电路中的反馈用分频器的分频比根据调制产生的调制数据而改变时调制器的轮廓以执行频率调制以扩展频谱，调制分布的转折点被移动以便分散频率，从而扩展频谱。此外，时钟发生电路由PLL电路和调制器构成，在调制器中提供多调制分布生成电路，并且调制曲线的转折点被移动以分散频率，使得扩频被重新传播。

7. 发明申请

US20060176933A1 Clock generating method and clock generating circuit 失效
公开(公告)号：US20060176933A1
公开(公告)日：2006-08-10
申请号：US11331154
申请日：2006-01-13
申请人： Yasuhiro Uemura , Takashi Nakamura , Akio Katsushima , Makoto Funatsu
发明人： Yasuhiro Uemura , Takashi Nakamura , Akio Katsushima , Makoto Funatsu
IPC分类号： H04B1/69 , H03D3/24
CPC分类号： H04B15/02 , H03C3/0925 , H03C3/0933 , H04B2215/067
摘要： In a clock generating circuit, while a PLL (Phase-Locked Loop) circuit and a modulator are employed, when a frequency dividing ratio of a feedback-purpose frequency divider in the PLL circuit is changed in accordance with modulation data produced based upon a modulation profile of the modulator to perform a frequency modulation so as to spread a spectrum, a turning point of the modulation profile is moved so as to disperse a degree of frequency, so that the spread spectrum is re-spread. Also, a clock generating circuit is constituted by a PLL circuit and a modulator, a multiple modulation profile generating circuit is provided in the modulator, and a turning point of a modulation profile is moved so as to disperse a degree of frequency, so that a spread spectrum is re-spread.

8. 发明授权

US5722160A Packaging method of BGA type electronic component 失效
标题翻译： BGA型电子元器件的封装方法
公开(公告)号：US5722160A
公开(公告)日：1998-03-03
申请号：US547811
申请日：1995-10-25
申请人： Yasuhiro Uemura , Masakazu Sakaue
发明人： Yasuhiro Uemura , Masakazu Sakaue
IPC分类号： H05K1/11 , H05K3/34 , H05K3/42
CPC分类号： H01L24/73 , H05K3/3436 , H01L2224/16237 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/351 , H05K1/11 , H05K2201/094 , H05K2201/10666 , H05K2203/0455 , H05K3/3431 , H05K3/3484 , H05K3/42 , Y02P70/613 , Y10T29/49144
摘要： A packaging method of an electronic component for packaging the electronic component to a packaging substrate comprises the steps of: forming a predetermined quantity of solder bumps at connection portions of the electronic component; forming through-holes and pads on the packaging substrate in such a manner as to correspond to the solder bumps; applying a solder paste to pad portions of the through-holes and the pads formed on the surface of the packaging substrate in such a manner as to attain a specific quantity of solder components with the predetermined quantity of the solder bump; and heating the electronic component and the packaging substrate to a predetermined temperature such that button-shaped connection bumps having a predetermined height are formed between the pads and the packaging substrate so as to connect the electronic component and the packaging substrate and to keep a predetermined gap between the electronic component and the packaging substrate, and cylindrical-post connection bumps are formed between the through-holes and the packaging substrate in accordance with this predetermined gap so as to connect the electronic component and the packaging substrate. In this way, the cylindrical-post connection bumps are formed in association with the button-shaped connection bumps.
摘要翻译：用于将电子部件封装到封装基板的电子部件的封装方法包括以下步骤：在电子部件的连接部形成规定量的焊料凸块; 以与所述焊料凸块相对应的方式在所述封装基板上形成通孔和焊盘; 以形成在所述封装基板的表面上的所述通孔和所述焊盘的焊盘部分的方式施加焊膏，以达到预定量的所述焊料凸块的特定量的焊料成分; 并且将电子部件和包装基板加热到预定温度，使得在焊盘和封装基板之间形成具有预定高度的按钮形连接凸块，以便连接电子部件和封装基板并保持预定的间隙在电子部件和包装基板之间，并且根据该预定间隙在通孔和封装基板之间形成圆柱形连接凸起，以连接电子部件和封装基板。以这种方式，圆柱形连接凸块与按钮形连接凸块相关联地形成。

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