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1. 发明授权

US06236681B1 Method for decoding MPEG compliant video bitstreams meeting 2-frame and letterboxing requirements 失效
标题翻译：解码满足2帧和letterboxing要求的MPEG兼容视频比特流的方法
公开(公告)号：US06236681B1
公开(公告)日：2001-05-22
申请号：US08904086
申请日：1997-07-31
申请人： Surya P. Varanasi , Tai Jing , Satish Soman
发明人： Surya P. Varanasi , Tai Jing , Satish Soman
IPC分类号： H04N718
CPC分类号： H04N19/42 , H04N7/0122 , H04N11/044 , H04N19/61 , H04N19/91
摘要： A system and method for decoding an MPEG video bitstream comprising several macroblocks of data is disclosed. The system comprises a macroblock core (MBCORE) which processes video bitstream data and computes discrete cosine transform data corresponding to the processed video bitstream, and a parser which parses the video bitstream macroblocks into multiple data blocks used in subsequent stages of decoding. The system further includes a transformation/motion compensation core (TMCCORE) which is divided into multiple stages. The TMCCORE includes an IDCT first stage, an intermediate memory (transpose RAM), and an IDCT second stage. The IDCT first stage passes data to memory and the IDCT second stage receives data from memory. The IDCT first stage has the ability to operate on a first data block while the second stage simultaneously operates on a second data block. The TMCCORE receives the discrete cosine transform data from the MBCORE and calculates and reconstructs a frame therefrom using motion compensation. The MBCORE can operate on data from a first macroblock while the TMCCORE simultaneously operates on data from a second macroblock. The TMCCORE has the ability to reconstruct a picture from the inverse discrete cosine transformed data and motion data received from the reference subsystem. The TMCCORE reconstructs the picture from one macroblock while the inverse discrete cosine transform first and second stages simultaneously operate on data from the macroblock. Alternately, reconstruction may occur while second stage processing and MBCORE functions occur.
摘要翻译：公开了一种用于解码包含几个数据块的MPEG视频比特流的系统和方法。该系统包括宏块核心（MBCORE），其处理视频比特流数据并计算对应于经处理的视频比特流的离散余弦变换数据，以及解析器，其将视频比特流宏块解析为在后续解码阶段中使用的多个数据块。该系统还包括被分成多个阶段的变换/运动补偿核心（TMCCORE）。 TMCCORE包括IDCT第一级，中间存储器（转置RAM）和IDCT第二级。 IDCT第一级将数据传送到存储器，IDCT第二级从存储器接收数据。 IDCT第一级具有在第一数据块上操作的能力，而第二级同时在第二数据块上操作。 TMCCORE从MBCORE接收离散余弦变换数据，并使用运动补偿来计算和重构一帧。 MBCORE可以对来自第一宏块的数据进行操作，同时TMCCORE同时对来自第二宏块的数据进行操作。 TMCCORE具有从参考子系统接收的反离散余弦变换数据和运动数据中重建图像的能力。 TMCCORE从一个宏块重建图像，而反相离散余弦变换第一和第二阶段同时对来自宏块的数据进行操作。或者，重建可能在第二阶段处理和MBCORE功能发生时发生。

2. 发明授权

US6122316A MPEG decoding system meeting 2-frame store and letterboxing requirements 失效
标题翻译： MPEG解码系统满足2帧存储和信箱要求
公开(公告)号：US6122316A
公开(公告)日：2000-09-19
申请号：US903809
申请日：1997-07-31
申请人： Surya P. Varanasi , Satish Soman , Tai Jing
发明人： Surya P. Varanasi , Satish Soman , Tai Jing
IPC分类号： G06T9/00 , H04N7/26 , H04N7/50 , H04N7/12 , H04B1/66
CPC分类号： H04N19/427 , H04N19/423 , H04N19/61
摘要： A system and method for decoding an MPEG video bitstream comprises, comprising a macroblock core (MBCORE) which processes video bitstream data and computes discrete cosine transform data and a parser which parses the video bitstream macroblocks into multiple data blocks used in subsequent stages of decoding. fixed length data words comprising variable length objects using a novel rotating register arrangement. A multistage transformation/motion compensation core (TMCCORE) uses intermediate memory. The IDCT first stage has the ability to operate on a first data block while the second stage simultaneously operates on a second data block. The TMCCORE receives the discrete cosine transform data from the MBCORE and calculates and reconstructs a frame therefrom using motion compensation. The MBCORE can operate on data from a first macroblock while the TMCCORE simultaneously operates on data from a second macroblock. The TMCCORE reconstructs the picture from one macroblock while the IDCT first and second stages simultaneously operate on data from the macroblock. Additionally, a horizontal and vertical half pixel compensation arrangement is included which has multiple adders and multiplexers.
摘要翻译：用于对MPEG视频比特流进行解码的系统和方法包括：处理视频比特流数据并计算离散余弦变换数据的宏块核心（MBCORE）以及将视频比特流宏块解析成在后续解码阶段中使用的多个数据块的解析器。使用新颖的旋转寄存器装置的包括可变长度对象的固定长度数据字。多级变换/运动补偿内核（TMCCORE）使用中间存储器。 IDCT第一级具有在第一数据块上操作的能力，而第二级同时在第二数据块上操作。 TMCCORE从MBCORE接收离散余弦变换数据，并使用运动补偿来计算和重构一帧。 MBCORE可以对来自第一宏块的数据进行操作，同时TMCCORE同时对来自第二宏块的数据进行操作。 TMCCORE从一个宏块重建图像，而IDCT第一和第二级同时对来自宏块的数据进行操作。此外，包括具有多个加法器和多路复用器的水平和垂直半像素补偿布置。

3. 发明授权

US06504871B1 IDCT processor for use in decoding MPEG compliant video bitstreams meeting 2-frame and letterboxing requirements 失效
标题翻译：用于解码MPEG兼容视频比特流的IDCT处理器，满足2帧和letterboxing要求
公开(公告)号：US06504871B1
公开(公告)日：2003-01-07
申请号：US08904085
申请日：1997-07-31
申请人： Surya P. Varanasi , Tai Jing
发明人： Surya P. Varanasi , Tai Jing
IPC分类号： H04N712
CPC分类号： G06F17/147 , H04N19/42 , H04N19/60 , H04N19/61
摘要： A system and method for performing an inverse discrete cosine transform (IDCT) based on DCT data is disclosed. The system is IEEE compliant and transforms one block (8×8) of pixels in 64 cycles. The IDCT processor receives the DCT input, produces the matrix (QXTQ)P, or XQP, in IDCT Stage 1 and stores the result in transpose RAM. IDCT Stage 2 performs the transpose of the result of IDCT Stage 1 and multiplies the result by P, completing the IDCT process and producing the IDCT output. The system performs the matrix function QXtQ, where X represents the DCT data and Q is a predetermined diagonal matrix. The resultant value is adjusted by discarding selected bits, and the system then postmultiplies this with the elements of a predetermined P matrix, and discards selected bits. The system performs a conversion and storing function and performs a sign change to obtain QXtQP. This completes first stage processing, which is then passed to transpose RAM. The system then initiates IDCT stage 2, and performs a matrix transpose of QXtQP, yielding (QXtQP)t. The system converts and clips data, and postmultiplies the result by the P matrix. Another conversion is performed, a buffer addition performed, and a sign switch occurs to obtain the elements of (QXtQP)tP. The system then right shifts the data seven bits, with roundoff, and not a clipping, and then truncates the result to between −256 and 255.
摘要翻译：公开了一种用于基于DCT数据执行逆离散余弦变换（IDCT）的系统和方法。该系统符合IEEE标准，并在64个周期内转换一个像素块（8x8）。 IDCT处理器接收DCT输入，在IDCT阶段1中产生矩阵（QXTQ）P或XQP，并将结果存储在转置RAM中。 IDCT阶段2执行IDCT阶段1的结果的转置，并将结果乘以P，完成IDCT处理并产生IDCT输出。系统执行矩阵函数QXtQ，其中X表示DCT数据，Q是预定的对角矩阵。通过舍弃所选位来调整结果值，然后系统将其与预定P矩阵的元素进行后乘数，并丢弃所选位。系统执行转换和存储功能，并执行符号更改以获取QXtQP。这完成了第一阶段处理，然后传递给转置RAM。然后系统启动IDCT阶段2，并执行QXtQP的矩阵转置，产生（QXtQP）t。系统转换和剪辑数据，并通过P矩阵对结果进行后乘数。进行另一转换，执行缓冲加法，并且发生符号切换以获得（QXtQP）tP的元素。然后，系统右侧将数据七位移位，并进行舍入，而不是裁剪，然后将结果截断到-256到255之间。

4. 发明授权

US06301304B1 Architecture and method for inverse quantization of discrete cosine transform coefficients in MPEG decoders 失效
标题翻译： MPEG解码器中离散余弦变换系数的逆量化的架构和方法
公开(公告)号：US06301304B1
公开(公告)日：2001-10-09
申请号：US09098657
申请日：1998-06-17
申请人： Tai Jing , Surya Varanasi
发明人： Tai Jing , Surya Varanasi
IPC分类号： H04N712
CPC分类号： H04N19/184 , H04N19/126 , H04N19/61
摘要： An inverse quantizer is provided with a reduced bit-width. In one embodiment, the inverse quantizer receives quantized DCT coefficients in sign+magnitude form with 1+11 bits of resolution, and produces reconstructed DCT coefficients with 1+11 bits of resolution. Although this is less than the theoretical minimum bit-width required to represent the entire reconstructed DCT coefficient range [−2048, 2047] mandated by the MPEG standard, certain IDCT implementations will maintain IEEE compliance when the −2048 value is replaced with −2047. (An example of one such implementation is provided in a co-pending application.) This reduces the range to [−2047, 2047]. In one embodiment, the inverse quantizer includes a dead-zone expander, a quantization multiplier, a mismatch controller, and a bit-width reducer. The dead-zone expander receives quantized coefficients with 1+11 bits of resolution, doubles them, and then increases their magnitude by one. The quantization multiplier multiplies the result by a 15 bit quantization matrix scale factor to produce reconstructed DCT coefficients. The mismatch controller modifies least significant bits of DCT coefficients according to the MPEG standard and limits the range of values for the DCT coefficients. Finally, the bit-width reducer converts the DCT coefficient representation to 1+11 bits.
摘要翻译：逆量化器具有减小的位宽。在一个实施例中，逆量化器以1 + 11位分辨率接收符号+幅度形式的量化DCT系数，并产生具有1 + 11位分辨率的重构DCT系数。尽管这不到表示由MPEG标准规定的整个重构DCT系数范围[-2048,2047]所需的理论最小位宽，但是当-2048值被-2047替换时，某些IDCT实现将维持IEEE的合规性。（一个这样的实现的示例在共同未决的应用中提供。）这将范围减小到[-2047,2047]。在一个实施例中，逆量化器包括死区扩展器，量化乘法器，失配控制器和位宽减小器。死区扩展器接收1 + 11位分辨率的量化系数，使其倍增，然后将其幅度增加1。量化乘法器将结果乘以15位量化矩阵比例因子以产生重构的DCT系数。不匹配控制器根据MPEG标准修改DCT系数的最低有效位并限制DCT系数的值的范围。最后，位宽减速器将DCT系数表示转换为1 + 11位。

5. 发明申请

US20130057325A1 AUTOMATIC FREQUENCY CALIBRATION OF A MULTI-LCVCO PHASE LOCKED LOOP WITH ADAPTIVE THRESHOLDS AND PROGRAMMABLE CENTER CONTROL VOLTAGE 失效
标题翻译：具有自适应阈值和可编程中心控制电压的多LCVCO相锁定环路的自动频率校准
公开(公告)号：US20130057325A1
公开(公告)日：2013-03-07
申请号：US13223418
申请日：2011-09-01
申请人： Yikui Jen Dong , Freeman Y. Zhong , Tai Jing , Chaitanya Palusa
发明人： Yikui Jen Dong , Freeman Y. Zhong , Tai Jing , Chaitanya Palusa
IPC分类号： H03L7/08 , H03L7/099
CPC分类号： H03L7/08
摘要： Described embodiments provide a method of calibrating, by a calibration engine, a phase-locked loop (PLL) having one or more adjustable oscillators. The method includes entering a calibration mode of the PLL. The PLL is set to an initial state, thereby selecting one of the adjustable oscillators for calibration, an initial threshold window, and an initial tuning band of the selected adjustable oscillator. If the control signal of the selected adjustable oscillator is not within the initial threshold window, the calibration engine iteratively adjusts at least one of: (i) the selected tuning band of the selected adjustable oscillator, (ii) the selected adjustable oscillator, and (iii) the selected threshold window until the control signal of the selected adjustable oscillator is within the adjusted threshold window. If the control signal is within the threshold window, the one or more calibration settings of the PLL are stored and used to set the PLL operation.
摘要翻译：所描述的实施例提供了一种通过校准引擎校准具有一个或多个可调节振荡器的锁相环（PLL）的方法。该方法包括进入PLL的校准模式。 PLL被设置为初始状态，从而选择用于校准的可调振荡器之一，初始阈值窗口和所选择的可调振荡器的初始调谐频带。如果所选择的可调节振荡器的控制信号不在初始阈值窗口内，则校准引擎迭代地调整以下至少一个：（i）所选择的可调节振荡器的选定调谐带，（ii）所选择的可调振荡器和（ iii）所选择的阈值窗口，直到所选择的可调节振荡器的控制信号在调整的阈值窗口内。如果控制信号在阈值窗口内，PLL的一个或多个校准设置被存储并用于设置PLL操作。

6. 发明授权

US08508308B2 Automatic frequency calibration of a multi-LCVCO phase locked loop with adaptive thresholds and programmable center control voltage 失效
标题翻译：具有自适应阈值和可编程中心控制电压的多LCVCO锁相环的自动频率校准
公开(公告)号：US08508308B2
公开(公告)日：2013-08-13
申请号：US13223418
申请日：2011-09-01
申请人： Yikui Jen Dong , Freeman Y. Zhong , Tai Jing , Chaitanya Palusa
发明人： Yikui Jen Dong , Freeman Y. Zhong , Tai Jing , Chaitanya Palusa
IPC分类号： H03L7/085
CPC分类号： H03L7/08
摘要： Described embodiments provide a method of calibrating, by a calibration engine, a phase-locked loop (PLL) having one or more adjustable oscillators. The method includes entering a calibration mode of the PLL. The PLL is set to an initial state, thereby selecting one of the adjustable oscillators for calibration, an initial threshold window, and an initial tuning band of the selected adjustable oscillator. If the control signal of the selected adjustable oscillator is not within the initial threshold window, the calibration engine iteratively adjusts at least one of: (i) the selected tuning band of the selected adjustable oscillator, (ii) the selected adjustable oscillator, and (iii) the selected threshold window until the control signal of the selected adjustable oscillator is within the adjusted threshold window. If the control signal is within the threshold window, the one or more calibration settings of the PLL are stored and used to set the PLL operation.
摘要翻译：所描述的实施例提供了一种通过校准引擎校准具有一个或多个可调节振荡器的锁相环（PLL）的方法。该方法包括进入PLL的校准模式。 PLL被设置为初始状态，从而选择用于校准的可调振荡器之一，初始阈值窗口和所选择的可调振荡器的初始调谐频带。如果所选择的可调节振荡器的控制信号不在初始阈值窗口内，则校准引擎迭代地调整以下至少一个：（i）所选择的可调节振荡器的选定调谐带，（ii）所选择的可调振荡器和（ iii）所选择的阈值窗口，直到所选择的可调节振荡器的控制信号在调整的阈值窗口内。如果控制信号在阈值窗口内，PLL的一个或多个校准设置被存储并用于设置PLL操作。

7. 发明授权

US07016410B2 Adaptive bit rate allocation 失效
标题翻译：自适应比特率分配
公开(公告)号：US07016410B2
公开(公告)日：2006-03-21
申请号：US10226531
申请日：2002-08-23
申请人： Michael Chang , Ying-Ming Wang , Tai Jing
发明人： Michael Chang , Ying-Ming Wang , Tai Jing
IPC分类号： H04N7/12
CPC分类号： G06T9/005 , H04N19/124 , H04N19/14 , H04N19/15 , H04N19/176 , H04N19/192
摘要： A method for determining quantization numbers for each macro block in one video segment having a prescribed capacity is disclosed. The quantization numbers determine how much data will be preserved for that macro block. The method begins by determining a level of complexity for each macro block. Next, initial quantization numbers are chosen for the macro blocks by choosing the largest values possible without exceeding the prescribed capacity of the video segment. Final quantization numbers are selected based on respective ones of the initial quantization numbers proportioned according to the level of complexity for that macro block. The final quantization numbers may be increased or decreased so that the capacity of the video segment is maximized but not exceeded.
摘要翻译：公开了一种用于确定具有规定容量的一个视频段中的每个宏块的量化数量的方法。量化数字确定为该宏块保留多少数据。该方法通过确定每个宏块的复杂程度开始。接下来，通过在不超过视频段的规定容量的情况下选择可能的最大值来为宏块选择初始量化数。基于根据该宏块的复杂度的比例的初始量化数的相应的一个，选择最终的量化数。可以增加或减少最终量化数，使得视频段的容量被最大化但不超过。

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