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1. 发明授权

US08582635B2 Sparse and reconfigurable floating tap feed forward equalization 有权
标题翻译：稀疏和可重新配置的浮动分接前馈均衡
公开(公告)号：US08582635B2
公开(公告)日：2013-11-12
申请号：US13410473
申请日：2012-03-02
申请人： Tomasz Prokop , Chaitanya Palusa
发明人： Tomasz Prokop , Chaitanya Palusa
IPC分类号： H03H7/30
CPC分类号： H04L25/03044
摘要： In described embodiments, a Floating Tap, Feed Forward Equalizer (FT-FFE) achieves performance comparable to a full size, long FFE when equalizing wire line channels in, for example, SerDes receivers. A FT-FFE might be employed as a standalone datapath equalizer, or might be employed in conjunction with other equalization techniques.
摘要翻译：在所描述的实施例中，浮动分接头，前馈均衡器（FT-FFE）在均衡例如SerDes接收机中的有线线路信道时实现与全尺寸长FFE相当的性能。 FT-FFE可以用作独立的数据路径均衡器，或者可以与其他均衡技术结合使用。

2. 发明申请

US20130230092A1 SPARSE AND RECONFIGURABLE FLOATING TAP FEED FORWARD EQUALIZATION 有权
标题翻译：稀疏和可重新配置的浮动平台进给正向均衡
公开(公告)号：US20130230092A1
公开(公告)日：2013-09-05
申请号：US13410473
申请日：2012-03-02
申请人： Tomasz Prokop , Chaitanya Palusa
发明人： Tomasz Prokop , Chaitanya Palusa
IPC分类号： H04L27/01
CPC分类号： H04L25/03044
摘要： In described embodiments, a Floating Tap, Feed Forward Equalizer (FT-FFE) achieves performance comparable to a full size, long FFE when equalizing wire line channels in, for example, SerDes receivers. A FT-FFE might be employed as a standalone datapath equalizer, or might be employed in conjunction with other equalization techniques.
摘要翻译：在所描述的实施例中，浮动分接头，前馈均衡器（FT-FFE）在均衡例如SerDes接收机中的有线线路信道时实现与全尺寸长FFE相当的性能。 FT-FFE可以用作独立的数据路径均衡器，或者可以与其他均衡技术结合使用。

3. 发明授权

US07027548B1 Delay settings for a wide-range, high-precision delay-locked loop and a delay locked loop implementation using these settings 失效
标题翻译：使用这些设置可实现宽范围，高精度延迟锁定环和延迟锁定环实现的延迟设置
公开(公告)号：US07027548B1
公开(公告)日：2006-04-11
申请号：US09873016
申请日：2001-05-30
申请人： Chaitanya Palusa , Abhijit Ray
发明人： Chaitanya Palusa , Abhijit Ray
IPC分类号： H03D3/24
CPC分类号： H03L7/0812 , H03D13/004 , H03L7/0891 , H03L7/091 , H03L7/10
摘要： A delay-locked-loop (DLL) that has increased precision and a wide range of operation is formed by utilizing a chain of delay blocks to add or subtract a discreet amount of delay, and a voltage-controlled delay line (VCDL) to add or subtract a smaller amount of delay. The delay blocks allow the delayed clock signal to get close to the reference clock signal, while the VCDL allows the delayed clock signal to lock onto the reference clock signal.
摘要翻译：通过利用一系列延迟块来增加或减少一定的延迟量来形成具有增加的精度和较宽的操作范围的延迟锁定环（DLL），以及电压控制的延迟线（VCDL）来添加或减去较小的延迟量。延迟块允许延迟的时钟信号接近参考时钟信号，而VCDL允许延迟的时钟信号锁定到参考时钟信号。

4. 发明授权

US08508308B2 Automatic frequency calibration of a multi-LCVCO phase locked loop with adaptive thresholds and programmable center control voltage 失效
标题翻译：具有自适应阈值和可编程中心控制电压的多LCVCO锁相环的自动频率校准
公开(公告)号：US08508308B2
公开(公告)日：2013-08-13
申请号：US13223418
申请日：2011-09-01
申请人： Yikui Jen Dong , Freeman Y. Zhong , Tai Jing , Chaitanya Palusa
发明人： Yikui Jen Dong , Freeman Y. Zhong , Tai Jing , Chaitanya Palusa
IPC分类号： H03L7/085
CPC分类号： H03L7/08
摘要： Described embodiments provide a method of calibrating, by a calibration engine, a phase-locked loop (PLL) having one or more adjustable oscillators. The method includes entering a calibration mode of the PLL. The PLL is set to an initial state, thereby selecting one of the adjustable oscillators for calibration, an initial threshold window, and an initial tuning band of the selected adjustable oscillator. If the control signal of the selected adjustable oscillator is not within the initial threshold window, the calibration engine iteratively adjusts at least one of: (i) the selected tuning band of the selected adjustable oscillator, (ii) the selected adjustable oscillator, and (iii) the selected threshold window until the control signal of the selected adjustable oscillator is within the adjusted threshold window. If the control signal is within the threshold window, the one or more calibration settings of the PLL are stored and used to set the PLL operation.
摘要翻译：所描述的实施例提供了一种通过校准引擎校准具有一个或多个可调节振荡器的锁相环（PLL）的方法。该方法包括进入PLL的校准模式。 PLL被设置为初始状态，从而选择用于校准的可调振荡器之一，初始阈值窗口和所选择的可调振荡器的初始调谐频带。如果所选择的可调节振荡器的控制信号不在初始阈值窗口内，则校准引擎迭代地调整以下至少一个：（i）所选择的可调节振荡器的选定调谐带，（ii）所选择的可调振荡器和（ iii）所选择的阈值窗口，直到所选择的可调节振荡器的控制信号在调整的阈值窗口内。如果控制信号在阈值窗口内，PLL的一个或多个校准设置被存储并用于设置PLL操作。

5. 发明授权

US06359470B1 Ultra low power voltage translation circuitry and its application in a TTL-to-CMOS buffer 有权
标题翻译：超低电压转换电路及其在TTL到CMOS缓冲器中的应用
公开(公告)号：US06359470B1
公开(公告)日：2002-03-19
申请号：US09735877
申请日：2000-12-13
申请人： Chaitanya Palusa
发明人： Chaitanya Palusa
IPC分类号： H03K17018
CPC分类号： H03K19/018521 , H03K19/0013
摘要： The power consumed by a voltage translator circuit, such as a TTL-to-CMOS buffer, is substantially reduced by changing the supply voltages provided to the input inverter. By reducing the supply voltage provided to the source of the p-channel transistor of the input inverter, the lowest logic-high TTL voltage applied to the gate turns off the p-channel transistor and turns on the n-channel transistor of the input inverter. By increasing the supply voltage provided to the source of the n-channel transistor of the input inverter, the highest logic-low TTL voltage applied to the gate turns off the n-channel transistor and turns on the p-channel transistor.
摘要翻译：通过改变提供给输入反相器的电源电压，电压转换器电路（例如TTL至CMOS缓冲器）消耗的功率大大降低。通过减少提供给输入反相器的p沟道晶体管源极的电源电压，施加到栅极的最低的逻辑高电压TTL电压关断p沟道晶体管，并导通输入反相器的n沟道晶体管。通过增加提供给输入反相器的n沟道晶体管源极的电源电压，施加到栅极的最高的逻辑低电压TTL电压关断n沟道晶体管并导通p沟道晶体管。

6. 发明授权

US08787439B2 Decision feedforward equalization 有权
标题翻译：前馈均衡
公开(公告)号：US08787439B2
公开(公告)日：2014-07-22
申请号：US13419009
申请日：2012-03-13
申请人： Chaitanya Palusa , Tomasz Prokop , Adam B. Healey , Ye Liu
发明人： Chaitanya Palusa , Tomasz Prokop , Adam B. Healey , Ye Liu
IPC分类号： H04L27/22
CPC分类号： H04L25/03057 , H04L27/02
摘要： In described embodiments, a Decision Feed Forward Equalizer (DFFE) comprises a hybrid architecture combining features of a Feed Forward Equalizer (FFE) and a Decision Feedback Equalizer (DFE). An exemplary DFFE offers relatively improved noise and crosstalk immunity than an FFE implementation alone, and relatively lower burst error propagation than a DFE implementation alone. The exemplary DFFE is a relatively simple implementation due few or no critical feedback paths, as compared to a DFE implementation alone. The exemplary DFFE allows for a parallel implementation of its DFE elements without an exponential increase in the hardware for higher numbers of taps. The exemplary DFFE allows for cascading, allowing for progressive improvement in BER, at relatively low implementation cost as a solution to achieve multi-tap DFE performance.
摘要翻译：在所描述的实施例中，决策前馈均衡器（DFFE）包括组合前馈均衡器（FFE）和判决反馈均衡器（DFE）的特征的混合架构。一个示例性的DFFE提供了比单独的FFE实现相对改进的噪声和串扰抗扰度，并且相比于单独的DFE实现相对较低的突发错误传播。与仅DFE实现相比，示例性DFFE是相对简单的实现，因为很少或没有关键的反馈路径。示例性DFFE允许其DFE元件的并行实现，而对于较高数量的抽头，硬件的指数增加。示例性DFFE允许级联，允许在相对低的实施成本下逐渐改进BER，作为实现多抽头DFE性能的解决方案。

7. 发明申请

US20130057325A1 AUTOMATIC FREQUENCY CALIBRATION OF A MULTI-LCVCO PHASE LOCKED LOOP WITH ADAPTIVE THRESHOLDS AND PROGRAMMABLE CENTER CONTROL VOLTAGE 失效
标题翻译：具有自适应阈值和可编程中心控制电压的多LCVCO相锁定环路的自动频率校准
公开(公告)号：US20130057325A1
公开(公告)日：2013-03-07
申请号：US13223418
申请日：2011-09-01
申请人： Yikui Jen Dong , Freeman Y. Zhong , Tai Jing , Chaitanya Palusa
发明人： Yikui Jen Dong , Freeman Y. Zhong , Tai Jing , Chaitanya Palusa
IPC分类号： H03L7/08 , H03L7/099
CPC分类号： H03L7/08
摘要： Described embodiments provide a method of calibrating, by a calibration engine, a phase-locked loop (PLL) having one or more adjustable oscillators. The method includes entering a calibration mode of the PLL. The PLL is set to an initial state, thereby selecting one of the adjustable oscillators for calibration, an initial threshold window, and an initial tuning band of the selected adjustable oscillator. If the control signal of the selected adjustable oscillator is not within the initial threshold window, the calibration engine iteratively adjusts at least one of: (i) the selected tuning band of the selected adjustable oscillator, (ii) the selected adjustable oscillator, and (iii) the selected threshold window until the control signal of the selected adjustable oscillator is within the adjusted threshold window. If the control signal is within the threshold window, the one or more calibration settings of the PLL are stored and used to set the PLL operation.
摘要翻译：所描述的实施例提供了一种通过校准引擎校准具有一个或多个可调节振荡器的锁相环（PLL）的方法。该方法包括进入PLL的校准模式。 PLL被设置为初始状态，从而选择用于校准的可调振荡器之一，初始阈值窗口和所选择的可调振荡器的初始调谐频带。如果所选择的可调节振荡器的控制信号不在初始阈值窗口内，则校准引擎迭代地调整以下至少一个：（i）所选择的可调节振荡器的选定调谐带，（ii）所选择的可调振荡器和（ iii）所选择的阈值窗口，直到所选择的可调节振荡器的控制信号在调整的阈值窗口内。如果控制信号在阈值窗口内，PLL的一个或多个校准设置被存储并用于设置PLL操作。

8. 发明授权

US06842032B2 IDDQ test methodology based on the sensitivity of fault current to power supply variations 失效
标题翻译：基于故障电流对电源变化灵敏度的IDDQ测试方法
公开(公告)号：US06842032B2
公开(公告)日：2005-01-11
申请号：US10684119
申请日：2003-10-10
申请人： Chaitanya Palusa
发明人： Chaitanya Palusa
IPC分类号： G01R31/30 , G01R31/26
CPC分类号： G01R31/3008
摘要： A method for testing integrated circuits is provided. The method includes providing an excitation voltage to a device, such as a MOSFET. A power supply voltage is also provided to the device, such as a drain to source voltage or VCC. The quiescent power supply current of the device is then measured, such as the IDDQ of the MOSFET. The power supply voltage to the device is then varied, and it is determined whether a change in the IDDQ of the device exceeds a predetermined allowable change.
摘要翻译：提供了一种用于测试集成电路的方法。该方法包括向诸如MOSFET的器件提供激发电压。还向器件提供电源电压，例如漏极到源极电压或VCC。然后测量器件的静态电源电流，例如MOSFET的IDDQ。然后改变到设备的电源电压，并且确定设备的IDDQ中的改变是否超过预定的允许变化。

9. 发明申请

US20130243066A1 DECISION FEEDFORWARD EQUALIZATION 有权
标题翻译：决策权衡均等化
公开(公告)号：US20130243066A1
公开(公告)日：2013-09-19
申请号：US13419009
申请日：2012-03-13
申请人： Chaitanya Palusa , Tomasz Prokop , Adam B. Healey , Ye Liu
发明人： Chaitanya Palusa , Tomasz Prokop , Adam B. Healey , Ye Liu
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04L27/02
摘要： In described embodiments, a Decision Feed Forward Equalizer (DFFE) comprises a hybrid architecture combining features of a Feed Forward Equalizer (FFE) and a Decision Feedback Equalizer (DFE). An exemplary DFFE offers relatively improved noise and crosstalk immunity than an FFE implementation alone, and relatively lower burst error propagation than a DFE implementation alone. The exemplary DFFE is a relatively simple implementation due few or no critical feedback paths, as compared to a DFE implementation alone. The exemplary DFFE allows for a parallel implementation of its DFE elements without an exponential increase in the hardware for higher numbers of taps. The exemplary DFFE allows for cascading, allowing for progressive improvement in BER, at relatively low implementation cost as a solution to achieve multi-tap DFE performance.
摘要翻译：在所描述的实施例中，决策前馈均衡器（DFFE）包括组合前馈均衡器（FFE）和判决反馈均衡器（DFE）的特征的混合架构。一个示例性的DFFE提供了比单独的FFE实现相对改进的噪声和串扰抗扰度，并且相比于单独的DFE实现相对较低的突发错误传播。与仅DFE实现相比，示例性DFFE是相对简单的实现，因为很少或没有关键的反馈路径。示例性DFFE允许其DFE元件的并行实现，而对于较高数量的抽头，硬件的指数增加。示例性DFFE允许级联，允许在相对低的实施成本下逐渐改进BER，作为实现多抽头DFE性能的解决方案。

10. 发明授权

US06664801B1 IDDQ test methodology based on the sensitivity of fault current to power supply variations 有权
标题翻译：基于故障电流对电源变化灵敏度的IDDQ测试方法
公开(公告)号：US06664801B1
公开(公告)日：2003-12-16
申请号：US09862045
申请日：2001-05-21
申请人： Chaitanya Palusa
发明人： Chaitanya Palusa
IPC分类号： G01R3126
CPC分类号： G01R31/3008
摘要： A method for testing integrated circuits is provided. The method includes providing an excitation voltage to a device, such as a MOSFET. A power supply voltage is also provided to the device, such as a drain to source voltage or VCC. The quiescent power supply current of the device is then measured, such as the IDDQ of the MOSFET. The power supply voltage to the device is then varied, and it is determined whether a change in the IDDQ of the device exceeds a predetermined allowable change.
摘要翻译：提供了一种用于测试集成电路的方法。该方法包括向诸如MOSFET的器件提供激发电压。还向器件提供电源电压，例如漏极到源极电压或VCC。然后测量器件的静态电源电流，例如MOSFET的IDDQ。然后改变到设备的电源电压，并且确定设备的IDDQ中的改变是否超过预定的允许变化。

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