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1. 发明授权

US08520958B2 Parallelization of variable length decoding 有权
公开(公告)号：US08520958B2
公开(公告)日：2013-08-27
申请号：US12702497
申请日：2010-02-09
申请人： Surinder Pal Singh , Aneesh Bhasin , Kaushik Saha
发明人： Surinder Pal Singh , Aneesh Bhasin , Kaushik Saha
IPC分类号： G06K9/36
CPC分类号： G06T9/005 , H03M7/40 , H04N19/436 , H04N19/44 , H04N19/46 , H04N19/91
摘要： Parallelization of decoding of a data stream encoded with a variable length code includes determining one or more markers, each of which indicates a position within the encoded data stream. The determined markers are included into the encoded data stream together with the encoded data. At the decoder side, the markers are parsed from the encoded data stream and based on the extracted markers. The encoded data is separated into partitions, which are decoded separately and in parallel.

2. 发明申请

US20110150351A1 PARALLELIZATION OF VARIABLE LENGTH DECODING 有权
标题翻译：可变长度解码的并行化
公开(公告)号：US20110150351A1
公开(公告)日：2011-06-23
申请号：US12702497
申请日：2010-02-09
申请人： Surinder Pal SINGH , Aneesh Bhasin , Kaushik Saha
发明人： Surinder Pal SINGH , Aneesh Bhasin , Kaushik Saha
IPC分类号： G06K9/36 , H03M7/40
CPC分类号： G06T9/005 , H03M7/40 , H04N19/436 , H04N19/44 , H04N19/46 , H04N19/91
摘要： Parallelization of decoding of a data stream encoded with a variable length code includes determining one or more markers, each of which indicates a position within the encoded data stream. The determined markers are included into the encoded data stream together with the encoded data. At the decoder side, the markers are parsed from the encoded data stream and based on the extracted markers. The encoded data is separated into partitions, which are decoded separately and in parallel.
摘要翻译：用可变长度码编码的数据流的解码的并行化包括确定一个或多个标记，每个标记表示编码数据流内的位置。确定的标记与编码数据一起被包括在编码数据流中。在解码器侧，从编码数据流中解析出标记，并根据提取的标记进行解析。编码数据被分成分开并且并行解码的分区。

3. 发明授权

US08587292B2 Power measurement circuit 有权
公开(公告)号：US08587292B2
公开(公告)日：2013-11-19
申请号：US12842256
申请日：2010-07-23
申请人： Surinder Pal Singh , Kaushik Saha
发明人： Surinder Pal Singh , Kaushik Saha
IPC分类号： G01R1/20
CPC分类号： H04L67/025 , G01R19/22 , G01R21/133 , H04L41/32
摘要： A system for power measurement in an electronic device includes a sensing unit, an analog-to-digital converter (ADC) and a controller. The sensing unit senses voltage across a power source and modulates a carrier signal based on the sensed voltage. The ADC converts a combination of the modulated carrier signal and audio signals received by the electronic device to generate a digitized combined signal and provides the digitized combined signal to the controller. The controller separates digitized modulated carrier signal and digitized audio signals. The digitized modulated carrier signal is demodulated to generate an output signal that provides a measure of the power consumed by the electronic device.

4. 发明授权

US08577179B2 Image processing arrangement illuminating regions of an image based on motion 有权
标题翻译：图像处理布置基于运动照射图像的区域
公开(公告)号：US08577179B2
公开(公告)日：2013-11-05
申请号：US12895629
申请日：2010-09-30
申请人： Surinder Pal Singh , Kaushik Saha , Sumit Johar
发明人： Surinder Pal Singh , Kaushik Saha , Sumit Johar
IPC分类号： G09G5/04
CPC分类号： G09G5/00 , G06T1/00
摘要： An image processing arrangement includes an input to receive an indicator of a power characteristic related to an image processing arrangement and an image processor to process an image based on the indicator of the power characteristic.
摘要翻译：图像处理装置包括用于接收与图像处理装置相关的功率特性的指示符的输入和基于功率特性的指标来处理图像的图像处理器。

5. 发明申请

US20120044226A1 IMAGE PROCESSING ARRANGEMENT 有权
标题翻译：图像处理装置
公开(公告)号：US20120044226A1
公开(公告)日：2012-02-23
申请号：US12895629
申请日：2010-09-30
申请人： Surinder Pal Singh , Kaushik Saha , Sumit Johar
发明人： Surinder Pal Singh , Kaushik Saha , Sumit Johar
IPC分类号： G09G5/00
CPC分类号： G09G5/00 , G06T1/00
摘要： An image processing arrangement includes an input to receive an indicator of a power characteristic related to an image processing arrangement and an image processor to process an image based on the indicator of the power characteristic.
摘要翻译：图像处理装置包括用于接收与图像处理装置相关的功率特性的指示符的输入和基于功率特性的指标来处理图像的图像处理器。

6. 发明授权

US08456197B2 Differential data sensing 有权
标题翻译：差分数据传感
公开(公告)号：US08456197B2
公开(公告)日：2013-06-04
申请号：US13118858
申请日：2011-05-31
申请人： Prashant Dubey , Navneet Gupta , Shailesh Kumar Pathak , Kaushik Saha , Gagandeep Singh Sachdev
发明人： Prashant Dubey , Navneet Gupta , Shailesh Kumar Pathak , Kaushik Saha , Gagandeep Singh Sachdev
IPC分类号： G01R19/00 , G11C7/00 , H03F3/45
CPC分类号： G11C7/065 , H04L25/0274
摘要： A first sensing circuit has input terminals coupled to a true differential signal line and a complementary differential signal line. A second sensing circuit also has input terminals coupled to said true signal and said complementary signal. Each sensing circuit has a true signal sensing path and a complementary signal sensing path. The first sensing circuit has an imbalance that is biased towards the complementary signal sensing path, while the second sensing circuit has an imbalance that is biased towards the true signal sensing path. Outputs from the first and second sensing circuits are processed by a logic circuit producing an output signal that is indicative of whether there a sufficient differential signal for sensing has been developed between the true differential signal line and the complementary differential signal line.
摘要翻译：第一感测电路具有耦合到真实差分信号线和互补差分信号线的输入端。第二感测电路还具有耦合到所述真实信号和所述互补信号的输入端子。每个感测电路具有真实的信号感测路径和互补信号感测路径。第一感测电路具有偏置于互补信号感测路径的不平衡，而第二感测电路具有被偏置到真实信号感测路径的不平衡。来自第一和第二感测电路的输出由逻辑电路处理，该逻辑电路产生一个输出信号，该输出信号指示在真实差分信号线和互补差分信号线之间是否存在足够的用于感测的差分信号。

7. 发明授权

US07489742B2 System and method for clock recovery in digital video communication 有权
标题翻译：数字视频通信中时钟恢复的系统和方法
公开(公告)号：US07489742B2
公开(公告)日：2009-02-10
申请号：US11254069
申请日：2005-10-19
申请人： Kaushik Saha , Chiranjib Chakraborty , Subrata Chatterjee
发明人： Kaushik Saha , Chiranjib Chakraborty , Subrata Chatterjee
IPC分类号： H04L27/00
CPC分类号： H04N21/4305
摘要： A system for clock recovery in digital video communication includes a delay measurement block for generating PCR input signals and for continuously determining the time interval between successive PCR input signals. The system also includes a first storage device for generating a first PCR signal corresponding to the time interval between arrival of successive PCR input signals and a PCR inter-arrival time computation filtering device to determine the average time of arrival difference between successive PCR packets. The system further includes an error correction device for minimizing error in the average PCR difference between successive PCR packets, a controlled system clock generator coupled to the output of the error correction device to generate system clock, a second storage device for generating a first system clock output, and a controlled clock period difference computation element for computing the clock period difference between the first and second system clock outputs. The controlled clock period difference computation element is coupled at its output to the error correction device to form a feedback circuit to minimize error between the system clock output and successive PCR differences.
摘要翻译：一种用于数字视频通信中的时钟恢复的系统包括用于产生PCR输入信号并连续地确定连续PCR输入信号之间的时间间隔的延迟测量块。该系统还包括：第一存储装置，用于产生对应于连续PCR输入信号到达之间的时间间隔的第一PCR信号和PCR到达间时间计算滤波装置，以确定连续PCR分组之间的平均到达时间差。所述系统还包括用于使连续的PCR分组之间的平均PCR差异的误差最小化的纠错装置，耦合到纠错装置的输出以产生系统时钟的受控系统时钟发生器，用于生成第一系统时钟的第二存储装置输出和用于计算第一和第二系统时钟输出之间的时钟周期差的受控时钟周期差计算元件。受控时钟周期差计算元件在其输出端耦合到纠错装置以形成反馈电路，以最小化系统时钟输出和连续PCR差异之间的误差。

8. 发明申请

US20050138098A1 FFT/IFFT processor 有权
标题翻译： FFT / IFFT处理器
公开(公告)号：US20050138098A1
公开(公告)日：2005-06-23
申请号：US11003924
申请日：2004-12-03
申请人： Kaushik Saha , Srijib Maiti , Marco Cornero
发明人： Kaushik Saha , Srijib Maiti , Marco Cornero
IPC分类号： G06F17/14 , G06F15/00
CPC分类号： G06F17/142
摘要： An FFT/IFFT processor having computation logic capable of processing butterfly operations, and storage for storing the operands of butterfly operations, including a mechanism for storing the operands of multiple consecutive butterfly operations in contiguous storage locations and wherein the computation logic is capable of simultaneously accessing and processing said multiple butterfly operations.
摘要翻译：具有能够处理蝶形运算的计算逻辑的FFT / IFFT处理器和用于存储蝶形运算操作数的存储器，包括用于在连续的存储位置存储多个连续的蝶形运算的操作数的机构，并且其中计算逻辑能够同时存取并处理所述多个蝴蝶操作。

9. 发明授权

US09197903B2 Method and system for determining a macroblock partition for data transcoding 有权
标题翻译：用于确定用于数据转码的宏块分区的方法和系统
公开(公告)号：US09197903B2
公开(公告)日：2015-11-24
申请号：US12253062
申请日：2008-10-16
申请人： Subarna Tripathi , Kaushik Saha , Emiliana Mario Picinelli
发明人： Subarna Tripathi , Kaushik Saha , Emiliana Mario Picinelli
IPC分类号： H04N7/12 , H04N19/59 , H04N19/176 , H04N19/196 , H04N19/103 , H04N19/40
CPC分类号： H04N19/59 , H04N19/103 , H04N19/176 , H04N19/196 , H04N19/40
摘要： A system and corresponding method determines a macroblock partition to transcode digital data from a first video standard to a second video standard with any spatial resolution. The system includes a processing module and an encoding module. The processing module processes digital data to determine a macroblock partition. The encoding module is coupled to the processing module for encoding the digital data based on the macroblock partition. The system is further coupled to a decoding module for receiving the digital data. The method determines the partition of a macroblock for transcoding digital data with any spatial resolution and without any motion estimation.
摘要翻译：系统和相应的方法确定宏块分区以将数字数据从第一视频标准转码为具有任何空间分辨率的第二视频标准。该系统包括处理模块和编码模块。处理模块处理数字数据以确定宏块分区。编码模块耦合到处理模块，用于基于宏块分区对数字数据进行编码。该系统进一步耦合到用于接收数字数据的解码模块。该方法确定用于使用任何空间分辨率对数字数据进行代码转换并且没有任何运动估计的宏块的分区。

10. 发明授权

US08711927B2 System and method for video encoding 有权
标题翻译：视频编码的系统和方法
公开(公告)号：US08711927B2
公开(公告)日：2014-04-29
申请号：US12636321
申请日：2009-12-11
申请人： Megha Agarwal , Sumit Johar , Kaushik Saha , Emiliano Mario Piccinelli
发明人： Megha Agarwal , Sumit Johar , Kaushik Saha , Emiliano Mario Piccinelli
IPC分类号： H04N7/26
CPC分类号： H04N19/48 , H04N19/115 , H04N19/149 , H04N19/152 , H04N19/172 , H04N19/176 , H04N19/18 , H04N19/61
摘要： An embodiment of the present disclosure relates to system comprises an encoding device. Said encoding device comprises a compression unit, a quantizer, a bit estimator, a bit rate encoder and a variable length encoder. An embodiment also is a method of encoding. Said method estimates a number of bits to encode a macroblock after compressing the data stream. Then the estimated bit encoded by a bit rate encoder and further quantized by the quantizer to get the final encoded bit stream. The number of bits required to encode a macroblock is estimated after the quantization process and before the encoding process. The macroblock bit estimator estimates the number of bits required to encode a particular macroblock depending on the quantized AC coefficients of that macroblock and the quantized AC coefficients of the neighboring frames normalized at a macroblock level.
摘要翻译：本公开的实施例涉及一种包括编码装置的系统。所述编码装置包括压缩单元，量化器，比特估计器，比特率编码器和可变长度编码器。实施例也是一种编码方法。所述方法估计在压缩数据流之后编码宏块的位数。然后估计比特由比特率编码器编码并由量化器进一步量化以获得最终的编码比特流。在量化处理之后和编码处理之前估计编码宏块所需的位数。宏块比特估计器根据该宏块的量化AC系数和在宏块级标准化的相邻帧的量化AC系数来估计对特定宏块进行编码所需的比特数。

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