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2. 发明授权

US07489742B2 System and method for clock recovery in digital video communication 有权
标题翻译：数字视频通信中时钟恢复的系统和方法
公开(公告)号：US07489742B2
公开(公告)日：2009-02-10
申请号：US11254069
申请日：2005-10-19
申请人： Kaushik Saha , Chiranjib Chakraborty , Subrata Chatterjee
发明人： Kaushik Saha , Chiranjib Chakraborty , Subrata Chatterjee
IPC分类号： H04L27/00
CPC分类号： H04N21/4305
摘要： A system for clock recovery in digital video communication includes a delay measurement block for generating PCR input signals and for continuously determining the time interval between successive PCR input signals. The system also includes a first storage device for generating a first PCR signal corresponding to the time interval between arrival of successive PCR input signals and a PCR inter-arrival time computation filtering device to determine the average time of arrival difference between successive PCR packets. The system further includes an error correction device for minimizing error in the average PCR difference between successive PCR packets, a controlled system clock generator coupled to the output of the error correction device to generate system clock, a second storage device for generating a first system clock output, and a controlled clock period difference computation element for computing the clock period difference between the first and second system clock outputs. The controlled clock period difference computation element is coupled at its output to the error correction device to form a feedback circuit to minimize error between the system clock output and successive PCR differences.
摘要翻译：一种用于数字视频通信中的时钟恢复的系统包括用于产生PCR输入信号并连续地确定连续PCR输入信号之间的时间间隔的延迟测量块。该系统还包括：第一存储装置，用于产生对应于连续PCR输入信号到达之间的时间间隔的第一PCR信号和PCR到达间时间计算滤波装置，以确定连续PCR分组之间的平均到达时间差。所述系统还包括用于使连续的PCR分组之间的平均PCR差异的误差最小化的纠错装置，耦合到纠错装置的输出以产生系统时钟的受控系统时钟发生器，用于生成第一系统时钟的第二存储装置输出和用于计算第一和第二系统时钟输出之间的时钟周期差的受控时钟周期差计算元件。受控时钟周期差计算元件在其输出端耦合到纠错装置以形成反馈电路，以最小化系统时钟输出和连续PCR差异之间的误差。

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