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1. 发明授权

US07187709B1 High speed configurable transceiver architecture 有权
标题翻译：高速可配置收发器架构
公开(公告)号：US07187709B1
公开(公告)日：2007-03-06
申请号：US10090250
申请日：2002-03-01
申请人： Suresh M. Menon , Atul V. Ghia , Warren E. Cory , Paul T. Sasaki , Philip M. Freidin , Santiago G. Asuncion , Philip D. Costello , Vasisht M. Vadi , Adebabay M. Bekele , Hare K. Verma
发明人： Suresh M. Menon , Atul V. Ghia , Warren E. Cory , Paul T. Sasaki , Philip M. Freidin , Santiago G. Asuncion , Philip D. Costello , Vasisht M. Vadi , Adebabay M. Bekele , Hare K. Verma
IPC分类号： H04B1/38 , H04L5/16
CPC分类号： G06F15/7867
摘要： One or more configurable transceivers can be fabricated on an integrated circuit. The transceivers contain various components having options that can be configured by turning configuration memory cells on or off. The integrated circuit may also contain programmable fabric. Other components in the transceivers can have options that are controlled by the programmable fabric. The integrated circuit may also contain one or more processor cores. The processor core and the transceivers can be connected by a plurality of signal paths that pass through the programmable fabric.
摘要翻译：一个或多个可配置的收发器可以在集成电路上制造。收发器包含各种组件，具有可通过打开或关闭配置存储单元来配置的选项。该集成电路还可以包含可编程织物。收发器中的其他组件可以具有由可编程结构控制的选项。集成电路还可以包含一个或多个处理器核。处理器核心和收发器可以通过通过可编程结构的多个信号路径连接。

2. 发明授权

US07111220B1 Network physical layer with embedded multi-standard CRC generator 有权
标题翻译：具有嵌入式多标准CRC发生器的网络物理层
公开(公告)号：US07111220B1
公开(公告)日：2006-09-19
申请号：US10090519
申请日：2002-03-01
申请人： Paul T. Sasaki , Suresh M. Menon , Atul V. Ghia , Warren E. Cory , Hare K. Verma , Philip M. Freidin
发明人： Paul T. Sasaki , Suresh M. Menon , Atul V. Ghia , Warren E. Cory , Hare K. Verma , Philip M. Freidin
IPC分类号： H03M13/00
CPC分类号： H03M13/091 , H03M13/6519 , H04L69/32 , H04L69/324
摘要： Disclosed are methods and structures for preparing data for transmission over a network. In an embodiment consistent with the OSI network model, transmit and receive CRC generators are moved from the link layer to the physical layer, which frees up valuable programmable logic resources when a programmable logic device is employed to perform the functions of the link layer. The CRC generators of the physical layer comply with a plurality of network communication standards.
摘要翻译：公开了用于准备通过网络传输的数据的方法和结构。在与OSI网络模型一致的实施例中，发送和接收CRC发生器从链路层移动到物理层，当使用可编程逻辑器件来执行链路层的功能时，发送和接收CRC发生器释放有价值的可编程逻辑资源。物理层的CRC生成器符合多个网络通信标准。

3. 发明授权

US06960933B1 Variable data width operation in multi-gigabit transceivers on a programmable logic device 有权
标题翻译：可编程逻辑器件上的千兆位收发器中的可变数据宽度操作
公开(公告)号：US06960933B1
公开(公告)日：2005-11-01
申请号：US10618146
申请日：2003-07-11
申请人： Warren E. Cory , Hare K. Verma , Atul V. Ghia , Paul T. Sasaki , Suresh M. Menon
发明人： Warren E. Cory , Hare K. Verma , Atul V. Ghia , Paul T. Sasaki , Suresh M. Menon
IPC分类号： H03K19/177 , H04L25/45
CPC分类号： H03K19/1774 , H03K19/17744 , H04L25/45
摘要： A transmit variable-width interface can be programmed to convert an electronic digital data path that is either 1N, 2N, 4N, or 8N bits wide into a data path that is 2N bits wide, either by serializing bits (4N- or 8N-bit cases), re-clocking bits (2N-bit case), or grouping bits (1N-bit case). A receive variable-width interface can be programmed to convert a data path 2N bits wide into a data path that is 1N, 2N, 4N, or 8N bits wide. The widths of the two variable-width data paths are controlled independently. The variable-width interfaces are coupled between a multi-gigabit transceiver and core logic of a programmable logic device. The incoming and outgoing data paths of the variable-width interfaces have separate clocks signals that are synchronized such that small amounts of skew in these clock signals do not disrupt the operation of the variable-width interfaces.
摘要翻译：传输可变宽度接口可编程为将1N，2N，4N或8N位宽的电子数字数据路径转换为2N位宽的数据通道，通过将位（4N或8N位）情况），重新计时位（2N位情况）或分组位（1N位情况）。接收可变宽度接口可以被编程为将2N位宽的数据路径转换成1N，2N，4N或8N位宽的数据路径。两个可变宽度数据路径的宽度被独立地控制。可变宽度接口耦合在可编程逻辑器件的千兆位收发器和核心逻辑之间。可变宽度接口的输入和输出数据路径具有同步的分离时钟信号，使得这些时钟信号中的少量偏移不会中断可变宽度接口的操作。

4. 发明授权

US06617877B1 Variable data width operation in multi-gigabit transceivers on a programmable logic device 有权
标题翻译：可编程逻辑器件上的千兆位收发器中的可变数据宽度操作
公开(公告)号：US06617877B1
公开(公告)日：2003-09-09
申请号：US10090286
申请日：2002-03-01
申请人： Warren E. Cory , Hare K. Verma , Atul V. Ghia , Paul T. Sasaki , Suresh M. Menon
发明人： Warren E. Cory , Hare K. Verma , Atul V. Ghia , Paul T. Sasaki , Suresh M. Menon
IPC分类号： H03K19177
CPC分类号： H03K19/1774 , H03K19/17744 , H04L25/45
摘要： A transmit variable-width interface can be programmed to convert an electronic digital data path that is either 1N, 2N, 4N, or 8N bits wide into a data path that is 2N bits wide, either by serializing bits (4N- or 8N-bit cases), re-clocking bits (2N-bit case), or grouping bits (1N-bit case). A receive variable-width interface can be programmed to convert a data path 2N bits wide into a data path that is 1N, 2N, 4N, or 8N bits wide. The widths of the two variable-width data paths are controlled independently. The variable-width interfaces are coupled between a multi-gigabit transceiver and core logic of a programmable logic device. The incoming and outgoing data paths of the variable-width interfaces have separate clocks signals that are synchronized such that small amounts of skew in these clock signals do not disrupt the operation of the variable-width interfaces.
摘要翻译：传输可变宽度接口可编程为将1N，2N，4N或8N位宽的电子数字数据路径转换为2N位宽的数据通道，通过将位（4N或8N位）情况），重新计时位（2N位情况）或分组位（1N位情况）。接收可变宽度接口可以被编程为将2N位宽的数据路径转换成1N，2N，4N或8N位宽的数据路径。两个可变宽度数据路径的宽度被独立地控制。可变宽度接口耦合在可编程逻辑器件的千兆位收发器和核心逻辑之间。可变宽度接口的输入和输出数据路径具有同步的分离时钟信号，使得这些时钟信号中的少量偏移不会中断可变宽度接口的操作。

5. 发明授权

US07099426B1 Flexible channel bonding and clock correction operations on a multi-block data path 有权
标题翻译：在多块数据路径上进行灵活的通道绑定和时钟校正操作
公开(公告)号：US07099426B1
公开(公告)日：2006-08-29
申请号：US10234978
申请日：2002-09-03
申请人： Warren E. Cory , Atul V. Ghia
发明人： Warren E. Cory , Atul V. Ghia
IPC分类号： H04L7/00
CPC分类号： G06F5/10 , G06F5/00 , H04J3/062 , H04L7/005
摘要： An elastic buffer for buffering a stream of data blocks includes a controller and a memory space, wherein multiple data blocks can be written and read during a single write or read clock cycle, respectively. Multiple read addresses are used for each read operation, allowing read access to non-contiguous memory locations during a single read cycle when desired. Therefore, the elastic buffer can perform clock correction and channel bonding operations on data streams that include correction and alignment data block sequences that do not match the width of the memory space. A stagger bit can be used to indicate the timing of read address adjustments during clock correction and channel bonding operations.
摘要翻译：用于缓冲数据块流的弹性缓冲器包括控制器和存储器空间，其中可以在单个写入或读取时钟周期期间分别写入和读取多个数据块。多个读取地址用于每个读取操作，允许在需要时在单个读取周期期间读取访问非连续的存储器位置。因此，弹性缓冲器可以对包括与存储器空间的宽度不匹配的校正和对准数据块序列的数据流执行时钟校正和信道绑定操作。可以使用错位来指示在时钟校正和通道绑定操作期间读地址调整的时序。

6. 发明授权

US07895509B1 Error checking parity and syndrome of a block of data with relocated parity bits 有权
标题翻译：错误检查具有重定位奇偶校验位的数据块的奇偶校验和校验
公开(公告)号：US07895509B1
公开(公告)日：2011-02-22
申请号：US12188935
申请日：2008-08-08
申请人： Warren E. Cory , David P. Schultz , Steven P. Young
发明人： Warren E. Cory , David P. Schultz , Steven P. Young
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： H03M13/27 , H03M13/19 , H03M13/45
摘要： Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.
摘要翻译：描述了用于错误检查信息的方法和装置。配置数据包括数据位和奇偶校验位。值得注意的是，可以重新定位奇偶校验位以确定校正子值。通过对配置数据的串行发送的每个字计算部分校正子值来确定综合征位，其中配置数据包括一个或多个数据向量。识别配置数据的每个单词的位置。确定部分综合征值是否是初始部分综合征值或响应于词位置的其他部分综合征值。存储初始部分综合征值，并且随后的部分综合征值被累积地添加到数据向量的每个单词以得到数据向量的校正子值。

7. 发明授权

US07623660B1 Method and system for pipelined decryption 有权
标题翻译：流水线解密的方法和系统
公开(公告)号：US07623660B1
公开(公告)日：2009-11-24
申请号：US11048443
申请日：2005-02-01
申请人： Warren E. Cory
发明人： Warren E. Cory
IPC分类号： B04N7/167
CPC分类号： H04L9/0637 , H04L2209/125
摘要： A method and system for pipelined decryption is disclosed. One embodiment includes a circuit having an iterative calculation section and a cipher text storage section in support of cipher block chaining (CBC) encryption mode. The iterative calculation section may be pipelined and configured to process multiple ciphertexts at once for increased throughput.
摘要翻译：公开了流水线解密的方法和系统。一个实施例包括具有支持密码块链接（CBC）加密模式的迭代计算部分和密文存储部分的电路。迭代计算部分可以被流水线化并被配置为一次处理多个密文以增加吞吐量。

8. 发明授权

US07382823B1 Channel bonding control logic architecture 有权
标题翻译：通道绑定控制逻辑架构
公开(公告)号：US07382823B1
公开(公告)日：2008-06-03
申请号：US10082490
申请日：2002-02-22
申请人： Warren E. Cory
发明人： Warren E. Cory
IPC分类号： H04B1/38
CPC分类号： H04L5/14
摘要： A design is used for coordinating channel bonding operations of a set of transceivers. The set include a master transceiver and a plurality of first level slave transceivers that perform channel bonding operations. Each first level transceiver is controlled by the master transceiver. The set also comprises a plurality of second level slave transceivers that perform channel bonding operations. Each second level transceiver is controlled by one of the plurality of first level transceivers. Any transceiver can be set as either a master, a first level slave or a second level slave. The design comprises a plurality of flip-flops and multiplexers, and is controlled by a MODE signal that determines the mode of operation of the design.
摘要翻译：一种设计用于协调一组收发器的信道绑定操作。该集合包括执行信道绑定操作的主收发器和多个第一级从属收发器。每个第一级收发器由主收发器控制。该集合还包括执行信道绑定操作的多个第二级从属收发器。每个第二级收发器由多个第一级收发器之一控制。任何收发器都可以设置为主机，第一级从机或二级从机。该设计包括多个触发器和多路复用器，并且由确定设计操作模式的MODE信号控制。

9. 发明授权

US07519747B1 Variable latency buffer and method of operation 有权
标题翻译：可变延迟缓冲器和操作方法
公开(公告)号：US07519747B1
公开(公告)日：2009-04-14
申请号：US10660449
申请日：2003-09-11
申请人： Warren E. Cory , Joseph Neil Kryzak
发明人： Warren E. Cory , Joseph Neil Kryzak
IPC分类号： G06F5/06 , G06F3/00 , G06F3/06
CPC分类号： G06F5/10
摘要： A variable latency elastic buffer comprises a plurality of memory locations in which to hold data. A write and read pointer may point to respective write and read addresses of the plurality of locations in which to write and read data. A controller may hold or increment the address of the read pointer upon determining that the amount of data within the buffer differs from a nominal fill level. In a particular embodiment, initialization circuitry may be operable to initialize the read and write addresses of the respective pointers responsive to an initialization request. The read and write addresses may differ from one another by an offset value equal to a value programmed for the nominal value.
摘要翻译：可变延迟弹性缓冲器包括在其中保存数据的多个存储器位置。写入和读取指针可以指向要写入和读取数据的多个位置的相应的写入和读取地址。在确定缓冲器中的数据量与标称填充水平不同的情况下，控制器可以保持或递增读取指针的地址。在特定实施例中，初始化电路可以用于响应于初始化请求来初始化各个指针的读取和写入地址。读取和写入地址可能彼此不同，偏移值等于为标称值编程的值。

10. 发明授权

US07088767B1 Method and apparatus for operating a transceiver in different data rates 有权
标题翻译：用于以不同数据速率操作收发器的方法和装置
公开(公告)号：US07088767B1
公开(公告)日：2006-08-08
申请号：US10090251
申请日：2002-03-01
申请人： Warren E. Cory
发明人： Warren E. Cory
IPC分类号： H04B1/38 , G06F13/38
CPC分类号： G06F13/385
摘要： A transceiver can be used to send and receive data at a lower data rate than the data rate its SERDES is designed to operate. It contains a transmitter interface that receives a first set of data at a lower data rate and delivers a second set of data to the SERDES at a higher data rate. The transceiver also contains a receiver interface that receives a third set of data from the SERDES at the higher data rate and delivers a fourth set of data at the lower data rate. To reduce the minimum transmission serial data rate, one embodiment of the present invention derives a half-speed clock for the transmitter interface. Using the half-speed clock, the transmitter interface supplies data to be transmitted at half the normal rate with respect to a reference clock. As a result, the data rate is reduced. The opposite operation is used for the receiver interface.
摘要翻译：收发器可用于以比SERDES设计的数据速率更低的数据速率发送和接收数据。它包含一个发射器接口，以较低的数据速率接收第一组数据，并以更高的数据速率向SERDES传送第二组数据。收发器还包含一个接收器接口，它以更高的数据速率从SERDES接收第三组数据，并以较低的数据速率传送第四组数据。为了降低最小传输串行数据速率，本发明的一个实施例为发射机接口导出半速时钟。使用半速时钟，发送器接口以相对于参考时钟的正常速率的一半传送数据。结果，数据速率降低。相反的操作用于接收器接口。

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