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1. 发明申请

US20090197036A1 Wood Flooring With Laminated Wood And HDF Using Symmetric Structure And Process For Manufacturing The Same 审中-公开
标题翻译：木地板与层压木材和HDF使用对称结构和制造过程相同
公开(公告)号：US20090197036A1
公开(公告)日：2009-08-06
申请号：US11628527
申请日：2006-07-25
申请人： Sung-chul Hwang , Jae-Wan Sung , Seung-Baik Nam , Seung-Hun Lee , Jong-Bum Kim , Bum-Soo Kim
发明人： Sung-chul Hwang , Jae-Wan Sung , Seung-Baik Nam , Seung-Hun Lee , Jong-Bum Kim , Bum-Soo Kim
IPC分类号： B32B3/06 , B32B27/40 , B32B38/04 , B32B21/08 , B32B21/04 , B32B37/12
CPC分类号： B32B21/14 , B32B3/06 , B32B7/02 , B32B7/12 , B32B21/02 , B32B21/042 , B32B21/13 , B32B2250/40 , B32B2255/08 , B32B2255/26 , B32B2307/584 , B32B2307/734 , B32B2419/04 , E04F15/02 , Y10T156/10 , Y10T156/1052 , Y10T428/24008 , Y10T428/31511 , Y10T428/31591 , Y10T428/31783 , Y10T428/3179 , Y10T428/31906 , Y10T428/31989
摘要： Disclosed is a wood flooring containing laminated wood and high-density fiberboard using a symmetric structure and a process for manufacturing the same. The wood flooring includes a high-density fiberboard core layer and an upper laminated wood layer and lower laminated wood or veneer layer symmetrically stacked about the high-density fiberboard core layer to achieve a stable structure, and the lower laminated wood or veneer layer has a density of 100±30% of that of the upper laminated wood layer to keep the balance therebetween. With this configuration it is possible to completely eliminate deformation problems caused by variation of environmental conditions such as temperature, humidity, etc., and to impart the natural texture of raw lumber and high durability to the flooring surface.
摘要翻译：公开了一种含有层叠木材和使用对称结构的高密度纤维板的木地板及其制造方法。木地板包括高密度纤维板芯层和上部层压木材层以及围绕高密度纤维板芯层对称地堆叠的下层叠木材或单板层以实现稳定的结构，并且下部层压木材或单板层具有密度为上层压木质层的100±30％，以保持它们之间的平衡。通过这种结构，能够完全消除由诸如温度，湿度等的环境条件的变化引起的变形问题，并赋予原木的自然纹理和对地板表面的高耐久性。

2. 发明申请

US20090049786A1 FLOORING HAVING TRANSFER-PRINTED HDF AND PROCESS FOR MANUFACTURING THE SAME 审中-公开
标题翻译：具有转印HDF的地板及其制造方法
公开(公告)号：US20090049786A1
公开(公告)日：2009-02-26
申请号：US11569820
申请日：2006-10-20
申请人： Sung-Chul Hwang , Seung-Baik Nam , Seung-Hun Lee , Jong-Bum Kim , Jae-Wan Sung
发明人： Sung-Chul Hwang , Seung-Baik Nam , Seung-Hun Lee , Jong-Bum Kim , Jae-Wan Sung
IPC分类号： E04F15/10 , B32B3/10 , B05D3/12 , E04B5/02
CPC分类号： B32B21/00 , Y10T428/24802 , Y10T428/24851
摘要： Disclosed herein is a low-priced flooring comprising a transfer-printed high-density fiberboard (HDF). According to the flooring, an aqueous primer layer is formed on a high-density fiberboard as a core layer and transfer printing is performed on the surface of the primer layer to form a printed layer so that the background fiber pattern of the high-density fiberboard is covered, the adhesion of the core layer to the printed layer is enhanced, and the natural beauty of wood is faithfully imparted to the surface of the flooring.
摘要翻译：本文公开了包括转印印刷的高密度纤维板（HDF）的低价地板。根据地板，在作为芯层的高密度纤维板上形成水性底漆层，在底漆层的表面进行转印，形成印刷层，使高密度纤维板的背景纤维图案被覆盖，芯层与印刷层的粘附性增强，木材的自然美丽被忠实地赋予了地板表面。

3. 发明授权

US08815672B2 Methods of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08815672B2
公开(公告)日：2014-08-26
申请号：US13223783
申请日：2011-09-01
申请人： Seung-Hun Lee , Byeong-Chan Lee , Sang-Bom Kang
发明人： Seung-Hun Lee , Byeong-Chan Lee , Sang-Bom Kang
IPC分类号： H01L21/8238
CPC分类号： H01L27/0922 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/02636 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/0629 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/7843
摘要： A method of manufacturing a semiconductor device includes forming first and second gate structures on a substrate in first and second regions, respectively, forming a first capping layer on the substrate by a first high density plasma process, such that the first capping layer covers the first and second gate structures except for sidewalls thereof, removing a portion of the first capping layer in the first region, removing an upper portion of the substrate in the first region using the first gate structure as an etching mask to form a first trench, and forming a first epitaxial layer to fill the first trench.
摘要翻译：一种制造半导体器件的方法包括分别在第一和第二区域的衬底上形成第一和第二栅极结构，通过第一高密度等离子体工艺在衬底上形成第一覆盖层，使得第一覆盖层覆盖第一以及除了其侧壁之外的第二栅极结构，去除第一区域中的第一覆盖层的一部分，使用第一栅极结构去除第一区域中的衬底的上部，以形成第一沟槽，并形成第一外延层，以填充第一沟槽。

4. 发明授权

US5889719A Semiconductor memory device 失效
公开(公告)号：US5889719A
公开(公告)日：1999-03-30
申请号：US511812
申请日：1995-08-07
申请人： Seung-Moon Yoo , Ejaz ul Haq , Yun-Ho Choi , Soo-In Cho , Dae-Je Chin , Nam-Soo Kang , Seung-Hun Lee
发明人： Seung-Moon Yoo , Ejaz ul Haq , Yun-Ho Choi , Soo-In Cho , Dae-Je Chin , Nam-Soo Kang , Seung-Hun Lee
IPC分类号： G11C5/14 , H02M3/07 , G11C13/00
CPC分类号： H02M3/07 , G11C5/145
摘要： A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.

5. 发明授权

US5838990A Circuit in a semiconductor memory for programming operation modes of the memory 失效
标题翻译：用于存储器的编程操作模式的半导体存储器中的电路
公开(公告)号：US5838990A
公开(公告)日：1998-11-17
申请号：US905562
申请日：1997-08-04
申请人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
发明人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/4076 , G11C11/408 , G11C11/409 , G06F9/00 , G06F13/16
CPC分类号： G11C7/1018 , G11C11/406 , G11C11/40618 , G11C11/4076 , G11C11/408 , G11C11/4082 , G11C11/4087 , G11C7/1045 , G11C7/1072 , G11C7/222 , G11C7/225 , G11C2207/2281
摘要： A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.
摘要翻译：能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于灭活信号在预充电循环中工作。

6. 发明授权

US5835956A Synchronous dram having a plurality of latency modes 失效
标题翻译：具有多个等待时间模式的同步电话
公开(公告)号：US5835956A
公开(公告)日：1998-11-10
申请号：US822148
申请日：1997-03-17
申请人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
发明人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/4076 , G11C11/408 , G11C11/409 , G06F13/16
CPC分类号： G11C7/1018 , G11C11/406 , G11C11/40618 , G11C11/4076 , G11C11/408 , G11C11/4082 , G11C11/4087 , G11C7/1045 , G11C7/1072 , G11C7/222 , G11C7/225 , G11C2207/2281
摘要： A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.
摘要翻译：能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于灭活信号在预充电循环中工作。

7. 发明授权

US5703828A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5703828A
公开(公告)日：1997-12-30
申请号：US580622
申请日：1995-12-29
申请人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
发明人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/4076 , G11C11/408 , G11C11/409 , G11C8/00
CPC分类号： G11C7/1018 , G11C11/406 , G11C11/40618 , G11C11/4076 , G11C11/408 , G11C11/4082 , G11C11/4087 , G11C7/1045 , G11C7/1072 , G11C7/222 , G11C7/225 , G11C2207/2281
摘要： A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.
摘要翻译：能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于灭活信号在预充电循环中工作。

8. 外观设计

USD421970S Personal computer unit 失效
公开(公告)号：USD421970S
公开(公告)日：2000-03-28
申请号：US100734
申请日：1999-02-17
申请人： Seung-Hun Lee
设计人： Seung-Hun Lee

9. 发明授权

US5631871A System for selecting one of a plurality of memory banks for use in an active cycle and all other banks for an inactive precharge cycle 失效
标题翻译：用于选择在活动周期中使用的多个存储体组中的一个并用于无效预充电循环的所有其它存储体的系统
公开(公告)号：US5631871A
公开(公告)日：1997-05-20
申请号：US578151
申请日：1995-12-29
申请人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
发明人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/4076 , G11C11/408 , G11C11/409 , B01F7/00 , B01F13/00
CPC分类号： G11C7/1018 , G11C11/406 , G11C11/40618 , G11C11/4076 , G11C11/408 , G11C11/4082 , G11C11/4087 , G11C7/1045 , G11C7/1072 , G11C7/222 , G11C7/225 , G11C2207/2281
摘要： A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.
摘要翻译：能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于灭活信号在预充电循环中工作。

10. 发明授权

US5598371A Data input/output sensing circuit of semiconductor memory device 失效
标题翻译：半导体存储器件的数据输入/输出检测电路
公开(公告)号：US5598371A
公开(公告)日：1997-01-28
申请号：US565292
申请日：1995-11-30
申请人： Ho-Cheol Lee , Seung-Hun Lee
发明人： Ho-Cheol Lee , Seung-Hun Lee
IPC分类号： G11C11/417 , G11C7/10 , G11C11/409 , G11C13/00 , G11C7/00
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/1078
摘要： A data input/output sensing circuit of a semiconductor memory device including a plurality of memory cells, the circuit comprises: input/output lines of the memory cell; data input/output terminals connected to outside of the memory cells; a single data input/output line connected between the input/output lines and the data input/output terminals; a sensing unit for sensing whether or not effective data is provided in the data input/output lines to thereby generate a sensing signal; an output driving unit for transmitting data of the data input/output lines to the data input/output terminals in response to the sensing signal; and a writing driving unit for inputting data of the data input/output terminals in response to the sensing signal.
摘要翻译：一种包括多个存储单元的半导体存储器件的数据输入/输出感测电路，该电路包括：存储单元的输入/输出线; 连接到存储单元外部的数据输入/输出端子; 连接在输入/输出线路和数据输入/输出端子之间的单个数据输入/输出线路; 感测单元，用于检测数据输入/输出线中是否提供有效数据，从而产生感测信号; 输出驱动单元，用于响应于感测信号将数据输入/输出线的数据发送到数据输入/输出端; 以及写入驱动单元，用于响应于感测信号输入数据输入/输出端子的数据。

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