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1. 发明授权

US07332386B2 Methods of fabricating fin field transistors 有权
标题翻译：散射场晶体管的制造方法
公开(公告)号：US07332386B2
公开(公告)日：2008-02-19
申请号：US11084922
申请日：2005-03-21
申请人： Chul Lee , Min-Sang Kim , Dong-gun Park , Choong-ho Lee , Chang-woo Oh , Jae-man Yoon , Dong-won Kim , Jeong-dong Choe , Ming Li , Hye-jin Cho
发明人： Chul Lee , Min-Sang Kim , Dong-gun Park , Choong-ho Lee , Chang-woo Oh , Jae-man Yoon , Dong-won Kim , Jeong-dong Choe , Ming Li , Hye-jin Cho
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238
CPC分类号： H01L29/785 , H01L21/26513 , H01L21/845 , H01L29/66795 , H01L29/78624
摘要： A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top of a portion of the fin. The gate insulation layer is between the gate electrode and the fin. The source region and the drain region in the fin and adjacent to opposite sides of the gate electrode. The source region of the fin has a different width than the drain region of the fin.
摘要翻译：翅片场效应晶体管（FinFET）包括衬底，鳍，栅电极，栅极绝缘层以及鳍中的源极和漏极区。翅片在基底上并沿着和垂直方向横向延伸。栅电极覆盖翅片的一侧和顶部。栅绝缘层位于栅电极和鳍之间。翅片中的源极区域和漏极区域，并且与栅电极的相对侧相邻。翅片的源极区域具有与鳍片的漏极区域不同的宽度。

2. 发明申请

US20050269629A1 Fin field effect transistors and methods of fabricating the same 有权
标题翻译： Fin场效应晶体管及其制造方法
公开(公告)号：US20050269629A1
公开(公告)日：2005-12-08
申请号：US11084922
申请日：2005-03-21
申请人： Chul Lee , Min-Sang Kim , Dong-gun Park , Choong-ho Lee , Chang-woo Oh , Jae-man Yoon , Dong-won Kim , Jeong-dong Choe , Ming Li , Hye-jin Cho
发明人： Chul Lee , Min-Sang Kim , Dong-gun Park , Choong-ho Lee , Chang-woo Oh , Jae-man Yoon , Dong-won Kim , Jeong-dong Choe , Ming Li , Hye-jin Cho
IPC分类号： H01L21/00 , H01L21/20 , H01L21/265 , H01L21/336 , H01L21/84 , H01L29/76 , H01L29/786 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L21/26513 , H01L21/845 , H01L29/66795 , H01L29/78624
摘要： A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top of a portion of the fin. The gate insulation layer is between the gate electrode and the fin. The source region and the drain region in the fin and adjacent to opposite sides of the gate electrode. The source region of the fin has a different width than the drain region of the fin.
摘要翻译：翅片场效应晶体管（FinFET）包括衬底，鳍，栅电极，栅极绝缘层以及鳍中的源极和漏极区。翅片在基底上并沿着和垂直方向横向延伸。栅电极覆盖翅片的一侧和顶部。栅绝缘层位于栅电极和鳍之间。翅片中的源极区域和漏极区域，并且与栅电极的相对侧相邻。翅片的源极区域具有与鳍片的漏极区域不同的宽度。

3. 发明授权

US07531412B2 Methods of manufacturing semiconductor memory devices including a vertical channel transistor 有权
标题翻译：制造包括垂直沟道晶体管的半导体存储器件的方法
公开(公告)号：US07531412B2
公开(公告)日：2009-05-12
申请号：US11151673
申请日：2005-06-13
申请人： Jae-man Yoon , Dong-gun Park , Choong-ho Lee , Moon-suk Yi , Chul Lee
发明人： Jae-man Yoon , Dong-gun Park , Choong-ho Lee , Moon-suk Yi , Chul Lee
IPC分类号： H01L21/336
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10814 , H01L27/10876 , H01L29/66666
摘要： Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.
摘要翻译：半导体存储器件包括在半导体衬底上具有间隔关系的半导体衬底和多个半导体材料柱。相邻的围绕电极围绕其中的一个柱。第一源极/漏极区域在相邻的柱之间的半导体衬底中，并且第二源极/漏极区域位于至少一个相邻支柱的上部。掩埋位线在第一源极/漏极区域中并且电耦合到第一源极/漏极区域，并且存储节点电极在相邻柱的至少一个的上部上并且与第二源极/漏极地区。

4. 发明授权

US08154065B2 Semiconductor memory devices including a vertical channel transistor having a buried bit line 有权
标题翻译：半导体存储器件包括具有埋入位线的垂直沟道晶体管
公开(公告)号：US08154065B2
公开(公告)日：2012-04-10
申请号：US12418879
申请日：2009-04-06
申请人： Jae-man Yoon , Dong-gun Park , Choong-ho Lee , Moon-suk Yi , Chul Lee
发明人： Jae-man Yoon , Dong-gun Park , Choong-ho Lee , Moon-suk Yi , Chul Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10814 , H01L27/10876 , H01L29/66666
摘要： Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.
摘要翻译：半导体存储器件包括在半导体衬底上具有间隔关系的半导体衬底和多个半导体材料柱。相邻的围绕电极围绕其中的一个柱。第一源极/漏极区域在相邻的柱之间的半导体衬底中，并且第二源极/漏极区域位于至少一个相邻支柱的上部。掩埋位线在第一源极/漏极区域中并且电耦合到第一源极/漏极区域，并且存储节点电极在相邻柱的至少一个的上部上并且与第二源极/漏极地区。

5. 发明申请

US20090189217A1 Semiconductor Memory Devices Including a Vertical Channel Transistor 有权
标题翻译：包括垂直通道晶体管的半导体存储器件
公开(公告)号：US20090189217A1
公开(公告)日：2009-07-30
申请号：US12418879
申请日：2009-04-06
申请人： Jae-man Yoon , Dong-gun Park , Choong-ho Lee , Moon-suk Yi , Chul Lee
发明人： Jae-man Yoon , Dong-gun Park , Choong-ho Lee , Moon-suk Yi , Chul Lee
IPC分类号： H01L29/78
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10814 , H01L27/10876 , H01L29/66666
摘要： Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.
摘要翻译：半导体存储器件包括在半导体衬底上具有间隔关系的半导体衬底和多个半导体材料柱。相邻的围绕电极围绕其中的一个柱。第一源极/漏极区域在相邻的柱之间的半导体衬底中，并且第二源极/漏极区域位于至少一个相邻支柱的上部。掩埋位线在第一源极/漏极区域中并且电耦合到第一源极/漏极区域，并且存储节点电极在相邻柱的至少一个的上部上并且与第二源极/漏极地区。

6. 发明申请

US20060097304A1 Semiconductor memory devices including a vertical channel transistor and methods of manufacturing the same 有权
标题翻译：包括垂直沟道晶体管的半导体存储器件及其制造方法
公开(公告)号：US20060097304A1
公开(公告)日：2006-05-11
申请号：US11151673
申请日：2005-06-13
申请人： Jae-man Yoon , Dong-gun Park , Choong-ho Lee , Moon-suk Yi , Chul Lee
发明人： Jae-man Yoon , Dong-gun Park , Choong-ho Lee , Moon-suk Yi , Chul Lee
IPC分类号： H01L29/94 , H01L21/20
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10814 , H01L27/10876 , H01L29/66666
摘要： Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.
摘要翻译：半导体存储器件包括在半导体衬底上具有间隔关系的半导体衬底和多个半导体材料柱。相邻的围绕电极围绕其中的一个柱。第一源极/漏极区域在相邻的柱之间的半导体衬底中，并且第二源极/漏极区域位于至少一个相邻支柱的上部。掩埋位线在第一源极/漏极区域中并且电耦合到第一源极/漏极区域，并且存储节点电极在相邻柱的至少一个的上部上并且与第二源极/漏极地区。

7. 发明申请

US20060141710A1 NOR-type flash memory device of twin bit cell structure and method of fabricating the same 审中-公开
标题翻译：双位单元结构的NOR型闪存器件及其制造方法
公开(公告)号：US20060141710A1
公开(公告)日：2006-06-29
申请号：US11311367
申请日：2005-12-20
申请人： Jae-man Yoon , Suk-kang Sung , Dong-gun Park , Choong-ho Lee , Tae-yong Kim
发明人： Jae-man Yoon , Suk-kang Sung , Dong-gun Park , Choong-ho Lee , Tae-yong Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568 , H01L29/7851
摘要： A NOR-type flash memory device comprises a plurality twin-bit memory cells arranged so that pairs of adjacent memory cells share a source/drain region and groups of four adjacent memory cells are electrically connected to each other by a single bitline contact.
摘要翻译： NOR型闪速存储器件包括多个双位存储器单元，其布置成使得相邻的存储单元对共享源极/漏极区域，并且四个相邻存储器单元的组通过单个位线接触彼此电连接。

8. 发明申请

US20100285645A1 METHODS OF MANUFACTURING VERTICAL CHANNEL SEMICONDUCTOR DEVICES 有权
标题翻译：制造垂直通道半导体器件的方法
公开(公告)号：US20100285645A1
公开(公告)日：2010-11-11
申请号：US12838826
申请日：2010-07-19
申请人： Jae-man Yoon , Dong-gun Park , Choong-Ho Lee , Seong-Goo Kim , Won-sok Lee , Seung-bae Park
发明人： Jae-man Yoon , Dong-gun Park , Choong-Ho Lee , Seong-Goo Kim , Won-sok Lee , Seung-bae Park
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L27/10823 , H01L27/10876 , H01L27/115 , H01L27/11568 , H01L28/91 , H01L29/66833 , H01L29/7926
摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.
摘要翻译：垂直沟道半导体器件包括具有上表面的柱的半导体衬底。绝缘栅电极围绕柱的周边。绝缘栅电极具有比柱的上表面低的垂直级的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。第一源极/漏极区域在与衬底相邻的衬底中。第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。接触焊盘接触柱的整个上表面以电连接到第二源/漏区。

9. 发明授权

US07586149B2 Circuit device including vertical transistors connected to buried bitlines and method of manufacturing the same 有权
标题翻译：电路装置包括连接到埋地位线的垂直晶体管及其制造方法
公开(公告)号：US07586149B2
公开(公告)日：2009-09-08
申请号：US11541756
申请日：2006-10-02
申请人： Jae-man Yoon , Dong-gun Park , Kang-yoon Lee , Choong-ho Lee , Bong-soo Kim , Seong-goo Kim , Hyeoung-won Seo , Seung-bae Park
发明人： Jae-man Yoon , Dong-gun Park , Kang-yoon Lee , Choong-ho Lee , Bong-soo Kim , Seong-goo Kim , Hyeoung-won Seo , Seung-bae Park
IPC分类号： H01L23/528 , H01L27/108
CPC分类号： H01L29/66666 , H01L21/823885 , H01L27/10876 , H01L27/10885 , H01L27/10894 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A circuit device including vertical transistors connected to buried bitlines and a method of manufacturing the circuit device. The circuit device includes a semiconductor substrate including a peripheral circuit region and left and right cell regions at both sides of the peripheral circuit region, bottom active regions arranged on the semiconductor substrate to be spaced apart from one another in a column direction and to extend from the peripheral circuit region alternately to the left cell region and the right cell region in a row direction, channel pillars protruding from the bottom active regions in a vertical direction and arranged to be aligned in the row direction and spaced apart from one another, gate electrodes provided with a gate dielectric layer and attached to surround side surfaces of the channel pillars, and buried bitlines extending along the bottom active regions, the bottom active regions including a bottom source/drain region.
摘要翻译：一种包括连接到掩埋位线的垂直晶体管的电路器件和制造该电路器件的方法。该电路装置包括半导体衬底，该半导体衬底包括外围电路区域和在外围电路区域的两侧的左侧和右侧电池区域，布置在半导体衬底上的底部有源区域在列方向上彼此间隔开并从所述外围电路区域与所述左侧单元区域和右侧单元区域交替地排列成行方向，所述通道柱从所述底部有源区域沿垂直方向突出并且被配置为在所述行方向上彼此对准并且彼此间隔开，栅电极设置有栅介电层并且被附接到环绕通道柱的侧表面，以及沿底部有源区延伸的掩埋位线，底部有源区包括底部源极/漏极区。

10. 发明申请

US20070075359A1 Circuit device including vertical transistors connected to buried bitlines and method of manufacturing the same 有权
标题翻译：电路装置包括连接到埋地位线的垂直晶体管及其制造方法
公开(公告)号：US20070075359A1
公开(公告)日：2007-04-05
申请号：US11541756
申请日：2006-10-02
申请人： Jae-man Yoon , Dong-gun Park , Kang-yoon Lee , Choong-ho Lee , Bong-soo Kim , Seong-goo Kim , Hyeoung-won Seo , Seung-bae Park
发明人： Jae-man Yoon , Dong-gun Park , Kang-yoon Lee , Choong-ho Lee , Bong-soo Kim , Seong-goo Kim , Hyeoung-won Seo , Seung-bae Park
IPC分类号： H01L21/8238
CPC分类号： H01L29/66666 , H01L21/823885 , H01L27/10876 , H01L27/10885 , H01L27/10894 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： In a circuit device including vertical transistors connected to buried bitlines and a method of manufacturing the circuit device, the circuit device includes a semiconductor substrate including a peripheral circuit region and left and right cell regions at both sides of the peripheral circuit region; bottom active regions arranged on the semiconductor substrate to be spaced apart from one another in a column direction and to extend from the peripheral circuit region alternately to the left cell region and the right cell region in a row direction; channel pillars protruding from the bottom active regions in a vertical direction and arranged to be aligned in the row direction and spaced apart from one another; gate electrodes provided with a gate dielectric layer and attached to surround side surfaces of the channel pillars; buried bitlines extending along the bottom active regions, the bottom active regions including a bottom source/drain region; local interconnection lines contacting side surfaces of the gate electrodes in the peripheral circuit region and extending between the gate electrodes to commonly interconnect the gate electrodes in the peripheral circuit region, thereby configuring a peripheral circuit; signal lines electrically connected to upper surfaces of the channel pillars or to at least one of the local interconnection lines; and interconnection contacts electrically connecting the local interconnection line to the buried bitline of a different row from that of the commonly-connected gate electrodes or electrically connecting the local interconnection lines to the signal lines, thereby configuring the peripheral circuit.
摘要翻译：在包括连接到掩埋位线的垂直晶体管的电路器件和制造电路器件的方法中，电路器件包括半导体衬底，该半导体衬底包括外围电路区域和外围电路区域两侧的左右单元区域; 布置在半导体衬底上的底部有源区域在列方向上彼此间隔开并且从外围电路区域交替地延伸到左小区区域和右小区区域在行方向上延伸; 通道柱从垂直方向从底部有源区域突出并且布置成在行方向上对齐并且彼此间隔开; 栅极电极设置有栅极电介质层并附接到环绕通道柱的侧表面; 掩埋位线沿着底部有源区延伸，底部有源区域包括底部源极/漏极区域; 局部互连线与外围电路区域中的栅电极的侧表面接触并在栅电极之间延伸，以在外围电路区域中共同连接栅电极，从而构成外围电路; 信号线电连接到通道柱的上表面或至少一个局部互连线; 以及互连触点将本地互连线电连接到与共用栅极电极的不同行的掩埋位线或将本地互连线电连接到信号线，从而配置外围电路。

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