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1. 发明授权

US08415224B2 Method of fabricating a semiconductor device including forming trenches having particular structures 有权
标题翻译：包括形成具有特定结构的沟槽的半导体器件的制造方法
公开(公告)号：US08415224B2
公开(公告)日：2013-04-09
申请号：US13184318
申请日：2011-07-15
申请人： Sung-Woo Hyun , Yu-Gyun Shin , Sun-Ghil Lee , Hong-Sik Yoon
发明人： Sung-Woo Hyun , Yu-Gyun Shin , Sun-Ghil Lee , Hong-Sik Yoon
IPC分类号： H01L21/331 , H01L21/76
CPC分类号： H01L27/088 , H01L21/823412 , H01L21/823418 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A method of fabricating a semiconductor device and a semiconductor device are provided. The method includes method of fabricating a semiconductor device including providing a semiconductor substrate having a first semiconductor device region and a second semiconductor device region defined therein, forming a first gate structure in the first semiconductor device region, forming a second gate structure in the second semiconductor device region, forming a first trench adjacent to a first side of the first gate structure, forming a second trench adjacent to a first side of the second gate structure, and forming a first semiconductor pattern in the first trench and forming a second semiconductor pattern in the second trench, wherein the first and second trenches have different cross-sectional shapes from each other.
摘要翻译：提供一种制造半导体器件和半导体器件的方法。该方法包括制造半导体器件的方法，该半导体器件包括提供具有限定在其中的第一半导体器件区域和第二半导体器件区域的半导体衬底，在第一半导体器件区域中形成第一栅极结构，在第二半导体中形成第二栅极结构形成与所述第一栅极结构的第一侧相邻的第一沟槽，形成邻近所述第二栅极结构的第一侧的第二沟槽，以及在所述第一沟槽中形成第一半导体图案并形成第二半导体图案第二沟槽，其中第一和第二沟槽彼此具有不同的横截面形状。

2. 发明申请

US20120049285A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120049285A1
公开(公告)日：2012-03-01
申请号：US13184318
申请日：2011-07-15
申请人： Sung-Woo Hyun , Yu-Gyun Shin , Sun-Ghil Lee , Hong-Sik Yoon
发明人： Sung-Woo Hyun , Yu-Gyun Shin , Sun-Ghil Lee , Hong-Sik Yoon
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L27/088 , H01L21/823412 , H01L21/823418 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A method of fabricating a semiconductor device and a semiconductor device are provided. The method includes method of fabricating a semiconductor device including providing a semiconductor substrate having a first semiconductor device region and a second semiconductor device region defined therein, forming a first gate structure in the first semiconductor device region, forming a second gate structure in the second semiconductor device region, forming a first trench adjacent to a first side of the first gate structure, forming a second trench adjacent to a first side of the second gate structure, and forming a first semiconductor pattern in the first trench and forming a second semiconductor pattern in the second trench, wherein the first and second trenches have different cross-sectional shapes from each other.
摘要翻译：提供一种制造半导体器件和半导体器件的方法。该方法包括制造半导体器件的方法，该半导体器件包括提供具有限定在其中的第一半导体器件区域和第二半导体器件区域的半导体衬底，在第一半导体器件区域中形成第一栅极结构，在第二半导体中形成第二栅极结构形成与所述第一栅极结构的第一侧相邻的第一沟槽，形成邻近所述第二栅极结构的第一侧的第二沟槽，以及在所述第一沟槽中形成第一半导体图案并形成第二半导体图案第二沟槽，其中第一和第二沟槽彼此具有不同的横截面形状。

3. 发明申请

US20100208508A1 Multi-level nonvolatile memory devices using variable resistive elements 有权
标题翻译：使用可变电阻元件的多级非易失性存储器件
公开(公告)号：US20100208508A1
公开(公告)日：2010-08-19
申请号：US12656754
申请日：2010-02-16
申请人： In-Gyu Baek , Hyun-Jun Sim , Hong-Sik Yoon , Jin-Shi Zhao , Min-Young Park
发明人： In-Gyu Baek , Hyun-Jun Sim , Hong-Sik Yoon , Jin-Shi Zhao , Min-Young Park
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/5685 , G11C13/0069 , G11C2013/0073 , G11C2211/5641 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/72
摘要： Multi-level nonvolatile memory devices using variable resistive elements, the multi-level nonvolatile memory devices including a word line, a bit line, and a multi-level memory cell coupled between the word line and the bit line, the multi-level memory cell having first resistance level and a second resistance level higher than the first resistance level when the first and second write biases having the same polarity are applied thereto, and a third resistance level and a fourth resistance level ranging between the first and second resistance levels, when third and fourth write biases having different polarities from each other are applied thereto.
摘要翻译：使用可变电阻元件的多级非易失性存储器件，多级非易失性存储器件包括字线，位线和耦合在字线和位线之间的多电平存储器单元，多电平存储器单元当施加具有相同极性的第一和第二写入偏置时，具有高于第一电阻电平的第一电阻电平和第二电阻电平，以及在第一和第二电阻电平之间范围内的第三电阻电平和第四电阻电平，当施加具有彼此不同极性的第三和第四写入偏置。

4. 发明申请

US20100155853A1 MULTIPLEXER AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：多路复用器及其制造方法
公开(公告)号：US20100155853A1
公开(公告)日：2010-06-24
申请号：US12641836
申请日：2009-12-18
申请人： Hong-Sik Yoon
发明人： Hong-Sik Yoon
IPC分类号： H01L27/105 , H03K17/00 , H01L21/77
CPC分类号： G11C7/1006 , G11C7/1012
摘要： A multiplexer can include a signal line arranged on a substrate and including a plurality of data wires extending in a first direction and electrically insulated from one another, where each of the data wires has at least one recess to provide at least two data wiring pieces. An address line is arranged on the signal line and includes a plurality of coding lines extending in a second direction different from the first direction and electrically insulated from the data wires. A plurality of switching elements are positioned in the recesses of the data wires and make electrical contact with the coding lines, where the switching element is configured to switch a data signal applied to the data wiring on and off in accordance with a coding signal applied to the coding lines, so that one of the data wires is selected according to a binary code of the address line corresponding to combinations of the coding lines to which coding signal is applied.
摘要翻译：多路复用器可以包括布置在基板上的信号线，并且包括在第一方向上延伸并且彼此电绝缘的多条数据线，其中每条数据线具有至少一个凹部以提供至少两条数据布线片。地址线布置在信号线上，并且包括沿与第一方向不同的第二方向延伸并与数据线电绝缘的多条编码线。多个开关元件位于数据线的凹部中并与编码线电接触，其中开关元件被配置为根据施加到数据线的编码信号来接通和断开施加到数据线的数据信号编码线，使得根据与应用了编码信号的编码线的组合对应的地址线的二进制码来选择数据线之一。

5. 发明申请

US20090289322A1 MEMORY DEVICES HAVING A CARBON NANOTUBE 有权
标题翻译：具有碳纳米管的存储器件
公开(公告)号：US20090289322A1
公开(公告)日：2009-11-26
申请号：US12469295
申请日：2009-05-20
申请人： Seong-Ho Moon , Hong-Sik Yoon , Subramanya Mayya , Sun-Woo Lee , Dong-Woo Kim , Xiaofeng Wang
发明人： Seong-Ho Moon , Hong-Sik Yoon , Subramanya Mayya , Sun-Woo Lee , Dong-Woo Kim , Xiaofeng Wang
IPC分类号： H01L29/872 , H01L23/52
CPC分类号： H01L27/1021 , B82Y10/00 , G11C13/025 , G11C23/00 , G11C2213/16 , H01L51/0048 , H01L51/057 , H01L51/0579
摘要： In a memory device having a carbon nanotube and a method of manufacturing the same, the memory device includes a lower electrode, an upper electrode having a first void exposing a sidewall of a diode therein, an insulating interlayer pattern having a second void exposing a portion of the lower electrode between the lower electrode and the upper electrode, and a carbon nanotube wiring capable of being electrically connected with the diode of the upper electrode by a voltage applied to the lower electrode. The memory device may reduce generation of a leakage current in a cross-bar memory.
摘要翻译：在具有碳纳米管的存储器件及其制造方法中，存储器件包括下电极，具有暴露其二极管侧壁的第一空隙的上电极，绝缘层间图案，具有暴露部分下电极和上电极之间的下电极，以及能够通过施加到下电极的电压与上电极的二极管电连接的碳纳米管布线。存储器件可以减少横条存储器中的漏电流的产生。

6. 发明申请

US20080029371A1 TRANSISTOR AND ITS METHOD OF MANUFACTURE 有权
标题翻译：晶体管及其制造方法
公开(公告)号：US20080029371A1
公开(公告)日：2008-02-07
申请号：US11832592
申请日：2007-08-01
申请人： Hong-Sik Yoon , Young-Moon Choi , Sun-Woo Lee
发明人： Hong-Sik Yoon , Young-Moon Choi , Sun-Woo Lee
IPC分类号： H01H57/00 , H01H11/00
CPC分类号： H01L51/057 , B82Y10/00 , H01L51/0048 , Y10T29/49105
摘要： An embodiment includes a transistor and a method of manufacturing the transistor that includes carbon nano-tubes. The physical behavior of the carbon nano-tubes, particularly a bending action that alters a normally linear configuration, is affected by elements of the transistor, such as a space between the carbon nano-tube and a conductor. The space is formed by removing a spacer. A dimension of the spacer between the carbon nano-tube and the conductor is efficiently controlled by adjusting its width. An operation voltage of the transistor relates to the physical behavior of the carbon nano-tubes, and thus to the dimensions of the spacer.
摘要翻译：实施例包括晶体管和制造包括碳纳米管的晶体管的方法。碳纳米管的物理行为，特别是改变正常线性构型的弯曲作用，受到晶体管的元件（例如碳纳米管和导体之间的空间）的影响。通过去除间隔物形成空间。通过调整碳纳米管和导体之间的间隔物的尺寸可有效地控制其宽度。晶体管的工作电压与碳纳米管的物理性能有关，因此与间隔物的尺寸有关。

7. 发明申请

US20060249770A1 Single Transistor Floating-Body DRAM Devices Having Vertical Channel Transistor Structures and Methods of Fabricating the Same 失效
标题翻译：具有垂直沟道晶体管结构的单晶体管浮动体DRAM器件及其制造方法
公开(公告)号：US20060249770A1
公开(公告)日：2006-11-09
申请号：US11380946
申请日：2006-05-01
申请人： Zong-Liang Huo , Seung-Jae Baik , In-Seok Yeo , Hong-Sik Yoon , Shi-Eun Kim
发明人： Zong-Liang Huo , Seung-Jae Baik , In-Seok Yeo , Hong-Sik Yoon , Shi-Eun Kim
IPC分类号： H01L21/8242
CPC分类号： H01L27/108 , H01L21/84 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： Single transistor floating-body DRAM devices have a vertical channel transistor structure. The DRAM devices include a substrate, and first and second floating bodies disposed on the substrate and isolated from each other. A source region and a drain region are disposed under and above each of the first and second floating bodies. A gate electrode is disposed between the first and second floating bodies. Methods of fabricating the single transistor floating-body DRAM devices are also provided.
摘要翻译：单晶体体浮体DRAM器件具有垂直沟道晶体管结构。 DRAM器件包括衬底，以及设置在衬底上并彼此隔离的第一和第二浮体。源极区域和漏极区域设置在第一和第二浮体的每一个之下和之上。栅电极设置在第一和第二浮体之间。还提供了制造单晶体管浮体DRAM器件的方法。

8. 发明授权

US08451645B2 Variable resistance memory devices and methods of programming variable resistance memory devices 有权
标题翻译：可变电阻存储器件和编程可变电阻存储器件的方法
公开(公告)号：US08451645B2
公开(公告)日：2013-05-28
申请号：US12851681
申请日：2010-08-06
申请人： Hong-Sik Yoon , Min-Young Park , In-Gyu Baek , Hyun-Jun Sim , Jin-Shi Zhao
发明人： Hong-Sik Yoon , Min-Young Park , In-Gyu Baek , Hyun-Jun Sim , Jin-Shi Zhao
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0064 , G11C2013/0066
摘要： A variable resistance memory device includes a variable resistance memory cell, and a by-pass circuit configured to electrically by-pass a programming pulse supplied to the variable resistance memory cell after a resistive state of the variable resistance memory cell has changed in response to the programming pulse.
摘要翻译：可变电阻存储器件包括可变电阻存储器单元和旁路电路，配置为在可变电阻存储单元的电阻状态响应于可变电阻存储单元的电阻状态发生变化之后，对提供给可变电阻存储单元的编程脉冲进行电旁路编程脉冲。

9. 发明授权

US08007875B2 Method of forming a carbon nano-tube 有权
标题翻译：形成碳纳米管的方法
公开(公告)号：US08007875B2
公开(公告)日：2011-08-30
申请号：US11832601
申请日：2007-08-01
申请人： Hong-Sik Yoon , Young-Moon Choi , Sun-Woo Lee
发明人： Hong-Sik Yoon , Young-Moon Choi , Sun-Woo Lee
IPC分类号： H05H1/24
CPC分类号： B82Y40/00 , B82Y30/00 , C01B32/162 , Y10S977/742
摘要： In a method of forming carbon nano-tubes, a catalytic film is formed on a substrate. The catalytic film is then transformed into preliminary catalytic particles. Thereafter, the preliminary catalytic particles are transformed into catalytic particles. Carbon nano-tubes then grow from the catalytic particles. The carbon nano-tubes have relatively high conductivity and high number density.
摘要翻译：在形成碳纳米管的方法中，在基板上形成催化膜。然后将催化膜转化成预催化颗粒。此后，将预催化剂颗粒转化成催化剂颗粒。碳纳米管然后从催化颗粒生长。碳纳米管具有较高的导电性和高密度。

10. 发明申请

US20110032747A1 VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF PROGRAMMING VARIABLE RESISTANCE MEMORY DEVICES 有权
标题翻译：可变电阻记忆体装置和编程可变电阻记忆装置的方法
公开(公告)号：US20110032747A1
公开(公告)日：2011-02-10
申请号：US12851681
申请日：2010-08-06
申请人： Hong-Sik Yoon , Min-Young Park , In-Gyu Baek , Hyun-Jun Sim , Jin-Shi Zhao
发明人： Hong-Sik Yoon , Min-Young Park , In-Gyu Baek , Hyun-Jun Sim , Jin-Shi Zhao
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0064 , G11C2013/0066
摘要： A variable resistance memory device includes a variable resistance memory cell, and a by-pass circuit configured to electrically by-pass a programming pulse supplied to the variable resistance memory cell after a resistive state of the variable resistance memory cell has changed in response to the programming pulse.
摘要翻译：可变电阻存储器件包括可变电阻存储器单元和旁路电路，配置为在可变电阻存储单元的电阻状态响应于可变电阻存储单元的电阻状态发生变化之后，对提供给可变电阻存储单元的编程脉冲进行电旁路编程脉冲。

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