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1. 发明申请

US20060138530A1 Non-volatile memory cell having a silicon-oxide-nitride-oxide-silicon gate structure and fabrication method of such cell 失效
标题翻译：具有氧化硅 - 氮化物 - 氧化物 - 硅栅极结构的非易失性存储单元和这种电池的制造方法
公开(公告)号：US20060138530A1
公开(公告)日：2006-06-29
申请号：US11357287
申请日：2006-02-16
申请人： Sung-Taeg Kang , Seung-Gyun Kim , Jung-Wook Han , Hyun-Khe Yoo
发明人： Sung-Taeg Kang , Seung-Gyun Kim , Jung-Wook Han , Hyun-Khe Yoo
IPC分类号： H01L29/792
CPC分类号： H01L21/28185 , G11C16/0466 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： A non-volatile memory cell able to be written in a first direction and read in a second direction is described. The memory cell includes one or two charge trapping regions located near either the source or the drain, or both the source and the drain. During a programming operation, electrons can be injected into the charge trapping region by hot electron injection. During an erasing operation, holes can be injected into the charge trapping region. Embodiments of the invention include a charge trapping region that is overlapped by the control gate only to an extent where the electrons that were injected during a programming operation can be erased later by injecting holes in the charge trapping region.
摘要翻译：描述能够沿第一方向写入并沿第二方向读取的非易失性存储单元。存储单元包括位于源极或漏极附近的一个或两个电荷捕获区域，或源极和漏极两者。在编程操作期间，可以通过热电子注入将电子注入电荷俘获区域。在擦除操作期间，可以将空穴注入电荷捕获区域。本发明的实施例包括与控制栅极重叠的电荷捕获区域，只有在编程操作期间注入的电子可以通过在电荷俘获区域中注入空穴而被擦除的程度。

2. 发明授权

US07042045B2 Non-volatile memory cell having a silicon-oxide nitride-oxide-silicon gate structure 失效
标题翻译：具有氧化硅 - 氧化物 - 氧化物 - 硅栅结构的非易失性存储单元
公开(公告)号：US07042045B2
公开(公告)日：2006-05-09
申请号：US10164943
申请日：2002-06-04
申请人： Sung-Taeg Kang , Seung-Gyun Kim , Jung-Wook Han , Hyun-Khe Yoo
发明人： Sung-Taeg Kang , Seung-Gyun Kim , Jung-Wook Han , Hyun-Khe Yoo
IPC分类号： H01L29/788
CPC分类号： H01L21/28185 , G11C16/0466 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： A non-volatile memory cell able to be written in a first direction and read in a second direction is described. The memory cell includes one or two charge trapping regions located near either the source or the drain, or both the source and the drain. During a programming operation, electrons can be injected into the charge trapping region by hot electron injection. During an erasing operation, holes can be injected into the charge trapping region. Embodiments of the invention include a charge trapping region that is overlapped by the control gate only to an extent where the electrons that were injected during a programming operation can be erased later by injecting holes in the charge trapping region.
摘要翻译：描述能够沿第一方向写入并沿第二方向读取的非易失性存储单元。存储单元包括位于源极或漏极附近的一个或两个电荷捕获区域，或源极和漏极两者。在编程操作期间，可以通过热电子注入将电子注入电荷俘获区域。在擦除操作期间，可以将空穴注入电荷捕获区域。本发明的实施例包括与控制栅极重叠的电荷捕获区域，只有在编程操作期间注入的电子可以通过在电荷俘获区域中注入空穴而被擦除的程度。

3. 发明申请

US20080020527A1 NON-VOLATILE MEMORY CELL HAVING A SILICON-OXIDE-NITRIDE-OXIDE-SILICON GATE STRUCTURE AND FABRICATION METHOD OF SUCH CELL 审中-公开
标题翻译：具有硅氧烷 - 氮氧化物 - 硅门结构的非挥发性记忆体和这种细胞的制造方法
公开(公告)号：US20080020527A1
公开(公告)日：2008-01-24
申请号：US11833132
申请日：2007-08-02
申请人： Sung-Taeg Kang , Seung-Gyun Kim , Jung-Wook Han , Hyun-Khe Yoo
发明人： Sung-Taeg Kang , Seung-Gyun Kim , Jung-Wook Han , Hyun-Khe Yoo
IPC分类号： H01L21/336
CPC分类号： H01L21/28185 , G11C16/0466 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/40117 , H01L29/4234 , H01L29/513 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： A non-volatile memory cell able to be written in a first direction and read in a second direction is described. The memory cell includes one or two charge trapping regions located near either the source or the drain, or both the source and the drain. During a programming operation, electrons can be injected into the charge trapping region by hot electron injection. During an erasing operation, holes can be injected into the charge trapping region. Embodiments of the invention include a charge trapping region that is overlapped by the control gate only to an extent where the electrons that were injected during a programming operation can be erased later by injecting holes in the charge trapping region.
摘要翻译：描述能够沿第一方向写入并沿第二方向读取的非易失性存储单元。存储单元包括位于源极或漏极附近的一个或两个电荷捕获区域，或源极和漏极两者。在编程操作期间，可以通过热电子注入将电子注入电荷俘获区域。在擦除操作期间，可以将空穴注入电荷捕获区域。本发明的实施例包括与控制栅极重叠的电荷捕获区域，只有在编程操作期间注入的电子可以通过在电荷俘获区域中注入空穴而被擦除的程度。

4. 发明授权

US07265410B2 Non-volatile memory cell having a silicon-oxide-nitride-oxide-silicon gate structure and fabrication method of such cell 失效
标题翻译：具有氧化硅 - 氮化物 - 氧化物 - 硅栅极结构的非易失性存储单元和这种电池的制造方法
公开(公告)号：US07265410B2
公开(公告)日：2007-09-04
申请号：US11357287
申请日：2006-02-16
申请人： Sung-Taeg Kang , Seung-Gyun Kim , Jung-Wook Han , Hyun-Khe Yoo
发明人： Sung-Taeg Kang , Seung-Gyun Kim , Jung-Wook Han , Hyun-Khe Yoo
IPC分类号： H01L29/788
CPC分类号： H01L21/28185 , G11C16/0466 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： A non-volatile memory cell able to be written in a first direction and read in a second direction is described. The memory cell includes one or two charge trapping regions located near either the source or the drain, or both the source and the drain. During a programming operation, electrons can be injected into the charge trapping region by hot electron injection. During an erasing operation, holes can be injected into the charge trapping region. Embodiments of the invention include a charge trapping region that is overlapped by the control gate only to an extent where the electrons that were injected during a programming operation can be erased later by injecting holes in the charge trapping region.
摘要翻译：描述能够沿第一方向写入并沿第二方向读取的非易失性存储单元。存储单元包括位于源极或漏极附近的一个或两个电荷捕获区域，或源极和漏极两者。在编程操作期间，可以通过热电子注入将电子注入电荷俘获区域。在擦除操作期间，可以将空穴注入电荷捕获区域。本发明的实施例包括与控制栅极重叠的电荷捕获区域，只有在编程操作期间注入的电子可以通过在电荷俘获区域中注入空穴而被擦除的程度。

5. 发明申请

US20070298571A1 Single chip data processing device with embedded nonvolatile memory and method thereof 失效
标题翻译：具有嵌入式非易失性存储器的单片数据处理装置及其方法
公开(公告)号：US20070298571A1
公开(公告)日：2007-12-27
申请号：US11896560
申请日：2007-09-04
申请人： Weon-Ho Park , Sang-Soo Kim , Hyun-Khe Yoo , Sung-Chul Park , Byoung-Ho Kim , Ju-Ri Kim , Seung-Beom Yoon , Jeong-Uk Han
发明人： Weon-Ho Park , Sang-Soo Kim , Hyun-Khe Yoo , Sung-Chul Park , Byoung-Ho Kim , Ju-Ri Kim , Seung-Beom Yoon , Jeong-Uk Han
IPC分类号： H01L21/8247
CPC分类号： H01L27/11526 , H01L21/76224 , H01L21/823842 , H01L21/823857 , H01L21/823892 , H01L27/0922 , H01L27/105 , H01L27/11546
摘要： A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant concentration, and a nonvolatile memory cell formed on the second well. A device is described comprising four wells of various conductivity types with a nonvolatile memory cell formed on the second well. A device is described comprising a plurality of wells for isolating transistors of a plurality of voltage ranges, wherein each one of the plurality of wells contains at least one transistor of a particular voltage range, and wherein transistors of only one of the plurality of voltage ranges are within each of the plurality of wells. A method is described of isolating transistors of a first voltage range from transistors of another voltage range, comprising forming a first well to hold transistors only of a first particular voltage range, and forming a second well to hold transistors only of a second particular voltage range.
摘要翻译：描述了一种器件，其包括具有第一掺杂剂浓度的第一导电类型的衬底，在衬底中形成的第一阱，在衬底中形成并且比第一阱更深的第一导电类型的第二阱，第二阱具有比第一掺杂剂浓度高的掺杂剂浓度，以及形成在第二阱上的非易失性存储单元。描述了一种装置，其包括具有形成在第二阱上的非易失性存储单元的各种导电类型的四个阱。描述了一种器件，其包括用于隔离多个电压范围的晶体管的多个阱，其中多个阱中的每一个阱包含特定电压范围的至少一个晶体管，并且其中仅一个电压范围的晶体管在多个孔的每一个内。描述了一种将第一电压范围的晶体管与另一电压范围的晶体管隔离的方法，包括形成第一阱以仅保持第一特定电压范围的晶体管，以及形成第二阱以仅将晶体管保持在第二特定电压范围。

6. 发明申请

US20070275509A1 Method of manufacturing NOR-type mask ROM device and semiconductor device including the same 失效
标题翻译：制造NOR型掩模ROM器件的方法和包括该器件的半导体器件
公开(公告)号：US20070275509A1
公开(公告)日：2007-11-29
申请号：US11882656
申请日：2007-08-03
申请人： Hyun-Khe Yoo , Weon-ho Park , Byoung-ho Kim
发明人： Hyun-Khe Yoo , Weon-ho Park , Byoung-ho Kim
IPC分类号： H01L21/8246
CPC分类号： H01L27/11266 , H01L21/823462 , H01L27/105 , H01L27/112 , H01L27/11293
摘要： A method of manufacturing a NOR-type mask ROM device includes forming a first gate electrode for an OFF cell and a second gate electrode for an ON cell on a semiconductor substrate of a first conductivity type. To code the mask ROM device, a plurality of source/drain regions is formed by implanting impurities of a second conductivity type, opposite the first conductivity type, into the semiconductor substrate adjacent only to one side of the first gate electrode and adjacent to both sides of the second gate electrode. To prevent misalignment of a bit line contact hole with a contact region, additional impurities are implanted only into a bit line contact region of the mask ROM device region. When a semiconductor device formed on the same substrate as the mask ROM device includes a double diffused region, additional implantation for both may be realized simultaneously.
摘要翻译：一种制造NOR型掩模ROM器件的方法包括在第一导电类型的半导体衬底上形成用于OFF电池的第一栅电极和用于ON电池的第二栅电极。为了对掩模ROM器件进行编码，通过将与第一导电类型相反的第二导电类型的杂质注入到仅与第一栅电极的一侧相邻并且邻近第二侧的半导体衬底中来形成多个源极/漏极区域的第二栅电极。为了防止与接触区域的位线接触孔不对准，仅将额外的杂质注入到掩模ROM器件区域的位线接触区域中。当形成在与掩模ROM器件相同的衬底上的半导体器件包括双扩散区域时，可以同时实现两者的附加注入。

7. 发明申请

US20050032288A1 Method of manufacturing NOR-type mask ROM device and semiconductor device including the same 失效
标题翻译：制造NOR型掩模ROM器件的方法和包括该器件的半导体器件
公开(公告)号：US20050032288A1
公开(公告)日：2005-02-10
申请号：US10899136
申请日：2004-07-27
申请人： Hyun-Khe Yoo , Weon-ho Park , Byoung-ho Kim
发明人： Hyun-Khe Yoo , Weon-ho Park , Byoung-ho Kim
IPC分类号： H01L21/8234 , H01L21/8246 , H01L27/105 , H01L27/112 , H01L21/336
CPC分类号： H01L27/11266 , H01L21/823462 , H01L27/105 , H01L27/112 , H01L27/11293
摘要： A method of manufacturing a NOR-type mask ROM device includes forming a first gate electrode for an OFF cell and a second gate electrode for an ON cell on a semiconductor substrate of a first conductivity type. To code the mask ROM device, a plurality of source/drain regions is formed by implanting impurities of a second conductivity type, opposite the first conductivity type, into the semiconductor substrate adjacent only to one side of the first gate electrode and adjacent to both sides of the second gate electrode. To prevent misalignment of a bit line contact hole with a contact region, additional impurities are implanted only into a bit line contact region of the mask ROM device region. When a semiconductor device formed on the same substrate as the mask ROM device includes a double diffused region, additional implantation for both may be realized simultaneously.
摘要翻译：一种制造NOR型掩模ROM器件的方法包括在第一导电类型的半导体衬底上形成用于OFF电池的第一栅电极和用于ON电池的第二栅电极。为了对掩模ROM器件进行编码，通过将与第一导电类型相反的第二导电类型的杂质注入到仅与第一栅电极的一侧相邻并且邻近第二侧的半导体衬底中来形成多个源极/漏极区域的第二栅电极。为了防止与接触区域的位线接触孔不对准，仅将额外的杂质注入到掩模ROM器件区域的位线接触区域中。当形成在与掩模ROM器件相同的衬底上的半导体器件包括双扩散区域时，可以同时实现两者的附加注入。

8. 发明授权

US07598139B2 Single chip data processing device with embedded nonvolatile memory and method thereof 失效
标题翻译：具有嵌入式非易失性存储器的单片数据处理装置及其方法
公开(公告)号：US07598139B2
公开(公告)日：2009-10-06
申请号：US11896560
申请日：2007-09-04
申请人： Weon-Ho Park , Sang-Soo Kim , Hyun-Khe Yoo , Sung-Chul Park , Byoung-Ho Kim , Ju-Ri Kim , Seung-Beom Yoon , Jeong-Uk Han
发明人： Weon-Ho Park , Sang-Soo Kim , Hyun-Khe Yoo , Sung-Chul Park , Byoung-Ho Kim , Ju-Ri Kim , Seung-Beom Yoon , Jeong-Uk Han
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L21/76224 , H01L21/823842 , H01L21/823857 , H01L21/823892 , H01L27/0922 , H01L27/105 , H01L27/11546
摘要： A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant concentration, and a nonvolatile memory cell formed on the second well. A device is described comprising four wells of various conductivity types with a nonvolatile memory cell formed on the second well. A device is described comprising a plurality of wells for isolating transistors of a plurality of voltage ranges, wherein each one of the plurality of wells contains at least one transistor of a particular voltage range, and wherein transistors of only one of the plurality of voltage ranges are within each of the plurality of wells. A method is described of isolating transistors of a first voltage range from transistors of another voltage range, comprising forming a first well to hold transistors only of a first particular voltage range, and forming a second well to hold transistors only of a second particular voltage range.
摘要翻译：描述了一种器件，其包括具有第一掺杂剂浓度的第一导电类型的衬底，在衬底中形成的第一阱，在衬底中形成并且比第一阱更深的第一导电类型的第二阱，第二阱具有比第一掺杂剂浓度高的掺杂剂浓度，以及形成在第二阱上的非易失性存储单元。描述了一种装置，其包括具有形成在第二阱上的非易失性存储单元的各种导电类型的四个阱。描述了一种器件，其包括用于隔离多个电压范围的晶体管的多个阱，其中多个阱中的每一个阱包含特定电压范围的至少一个晶体管，并且其中仅一个电压范围的晶体管在多个孔的每一个内。描述了一种将第一电压范围的晶体管与另一电压范围的晶体管隔离的方法，包括形成第一阱以仅保持第一特定电压范围的晶体管，以及形成第二阱以仅将晶体管保持在第二特定电压范围。

9. 发明申请

US20080076242A1 Method of fabricating nonvolatile memory device 审中-公开
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20080076242A1
公开(公告)日：2008-03-27
申请号：US11893063
申请日：2007-08-14
申请人： Sung-Gon Choi , Hyun-Khe Yoo , Bo-Young Seo , Chang-Min Jeon , Ji-Do Ryu
发明人： Sung-Gon Choi , Hyun-Khe Yoo , Bo-Young Seo , Chang-Min Jeon , Ji-Do Ryu
IPC分类号： H01L21/3205
CPC分类号： H01L27/11526 , H01L27/11546
摘要： A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate having a cell array region and a peripheral circuit region. Cell gate patterns are formed in the cell array region, and peripheral gate patterns are formed in the peripheral circuit region. Each of the cell gate patterns includes a control gate pattern and a capping pattern, and each of the peripheral gate patterns has a smaller thickness than the cell gate pattern. An interlayer dielectric layer is formed on the resultant structure having the cell gate patterns and the peripheral gate patterns. The interlayer dielectric layer is planarized by etching until the top surface of the capping pattern is exposed, so that an interlayer dielectric pattern is formed. The interlayer dielectric pattern covers the peripheral circuit region and fills a space between the cell gate patterns. An ion implantation process is performed using the interlayer dielectric pattern as an ion mask so that impurity ions are selectively implanted into the control gate pattern.
摘要翻译：制造非易失性存储器件的方法包括制备具有单元阵列区域和外围电路区域的半导体衬底。在单元阵列区域中形成单元栅极图案，并且在外围电路区域中形成外围栅极图案。每个单元栅极图案包括控制栅极图案和封盖图案，并且每个外围栅极图案具有比单元栅极图案更小的厚度。在具有单元栅极图案和外围栅极图案的合成结构上形成层间介电层。通过蚀刻来平坦化层间绝缘层，直到覆盖图案的顶表面露出，形成层间电介质图案。层间电介质图案覆盖外围电路区域并填充单元栅极图案之间的空间。使用层间电介质图案作为离子掩模进行离子注入工艺，使得杂质离子被选择性地注入到控制栅极图案中。

10. 发明授权

US06914290B2 Split-gate type nonvolatile memory devices 失效
标题翻译：分闸式非易失性存储器件
公开(公告)号：US06914290B2
公开(公告)日：2005-07-05
申请号：US10330425
申请日：2002-12-30
申请人： Hyun-Khe Yoo , Jeong-Uk Han
发明人： Hyun-Khe Yoo , Jeong-Uk Han
IPC分类号： H01L27/10 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115 , H01L27/11524
摘要： The nonvolatile memory device includes an electrically programmable transistor and a selection transistor. The selection transistor is connected between the electrically program transistor and a programmable voltage supply line. The selection transistor controls application of a voltage on the program voltage supply line to the electrically programmable transistor.
摘要翻译：非易失性存储器件包括电可编程晶体管和选择晶体管。选择晶体管连接在电子程序晶体管和可编程电压电源线之间。选择晶体管控制将编程电压供应线上的电压施加到电可编程晶体管。

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