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1. 发明申请

US20070298571A1 Single chip data processing device with embedded nonvolatile memory and method thereof 失效
标题翻译：具有嵌入式非易失性存储器的单片数据处理装置及其方法
公开(公告)号：US20070298571A1
公开(公告)日：2007-12-27
申请号：US11896560
申请日：2007-09-04
申请人： Weon-Ho Park , Sang-Soo Kim , Hyun-Khe Yoo , Sung-Chul Park , Byoung-Ho Kim , Ju-Ri Kim , Seung-Beom Yoon , Jeong-Uk Han
发明人： Weon-Ho Park , Sang-Soo Kim , Hyun-Khe Yoo , Sung-Chul Park , Byoung-Ho Kim , Ju-Ri Kim , Seung-Beom Yoon , Jeong-Uk Han
IPC分类号： H01L21/8247
CPC分类号： H01L27/11526 , H01L21/76224 , H01L21/823842 , H01L21/823857 , H01L21/823892 , H01L27/0922 , H01L27/105 , H01L27/11546
摘要： A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant concentration, and a nonvolatile memory cell formed on the second well. A device is described comprising four wells of various conductivity types with a nonvolatile memory cell formed on the second well. A device is described comprising a plurality of wells for isolating transistors of a plurality of voltage ranges, wherein each one of the plurality of wells contains at least one transistor of a particular voltage range, and wherein transistors of only one of the plurality of voltage ranges are within each of the plurality of wells. A method is described of isolating transistors of a first voltage range from transistors of another voltage range, comprising forming a first well to hold transistors only of a first particular voltage range, and forming a second well to hold transistors only of a second particular voltage range.
摘要翻译：描述了一种器件，其包括具有第一掺杂剂浓度的第一导电类型的衬底，在衬底中形成的第一阱，在衬底中形成并且比第一阱更深的第一导电类型的第二阱，第二阱具有比第一掺杂剂浓度高的掺杂剂浓度，以及形成在第二阱上的非易失性存储单元。描述了一种装置，其包括具有形成在第二阱上的非易失性存储单元的各种导电类型的四个阱。描述了一种器件，其包括用于隔离多个电压范围的晶体管的多个阱，其中多个阱中的每一个阱包含特定电压范围的至少一个晶体管，并且其中仅一个电压范围的晶体管在多个孔的每一个内。描述了一种将第一电压范围的晶体管与另一电压范围的晶体管隔离的方法，包括形成第一阱以仅保持第一特定电压范围的晶体管，以及形成第二阱以仅将晶体管保持在第二特定电压范围。

2. 发明授权

US07598139B2 Single chip data processing device with embedded nonvolatile memory and method thereof 失效
标题翻译：具有嵌入式非易失性存储器的单片数据处理装置及其方法
公开(公告)号：US07598139B2
公开(公告)日：2009-10-06
申请号：US11896560
申请日：2007-09-04
申请人： Weon-Ho Park , Sang-Soo Kim , Hyun-Khe Yoo , Sung-Chul Park , Byoung-Ho Kim , Ju-Ri Kim , Seung-Beom Yoon , Jeong-Uk Han
发明人： Weon-Ho Park , Sang-Soo Kim , Hyun-Khe Yoo , Sung-Chul Park , Byoung-Ho Kim , Ju-Ri Kim , Seung-Beom Yoon , Jeong-Uk Han
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L21/76224 , H01L21/823842 , H01L21/823857 , H01L21/823892 , H01L27/0922 , H01L27/105 , H01L27/11546
摘要： A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant concentration, and a nonvolatile memory cell formed on the second well. A device is described comprising four wells of various conductivity types with a nonvolatile memory cell formed on the second well. A device is described comprising a plurality of wells for isolating transistors of a plurality of voltage ranges, wherein each one of the plurality of wells contains at least one transistor of a particular voltage range, and wherein transistors of only one of the plurality of voltage ranges are within each of the plurality of wells. A method is described of isolating transistors of a first voltage range from transistors of another voltage range, comprising forming a first well to hold transistors only of a first particular voltage range, and forming a second well to hold transistors only of a second particular voltage range.
摘要翻译：描述了一种器件，其包括具有第一掺杂剂浓度的第一导电类型的衬底，在衬底中形成的第一阱，在衬底中形成并且比第一阱更深的第一导电类型的第二阱，第二阱具有比第一掺杂剂浓度高的掺杂剂浓度，以及形成在第二阱上的非易失性存储单元。描述了一种装置，其包括具有形成在第二阱上的非易失性存储单元的各种导电类型的四个阱。描述了一种器件，其包括用于隔离多个电压范围的晶体管的多个阱，其中多个阱中的每一个阱包含特定电压范围的至少一个晶体管，并且其中仅一个电压范围的晶体管在多个孔的每一个内。描述了一种将第一电压范围的晶体管与另一电压范围的晶体管隔离的方法，包括形成第一阱以仅保持第一特定电压范围的晶体管，以及形成第二阱以仅将晶体管保持在第二特定电压范围。

3. 发明授权

US06914290B2 Split-gate type nonvolatile memory devices 失效
标题翻译：分闸式非易失性存储器件
公开(公告)号：US06914290B2
公开(公告)日：2005-07-05
申请号：US10330425
申请日：2002-12-30
申请人： Hyun-Khe Yoo , Jeong-Uk Han
发明人： Hyun-Khe Yoo , Jeong-Uk Han
IPC分类号： H01L27/10 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115 , H01L27/11524
摘要： The nonvolatile memory device includes an electrically programmable transistor and a selection transistor. The selection transistor is connected between the electrically program transistor and a programmable voltage supply line. The selection transistor controls application of a voltage on the program voltage supply line to the electrically programmable transistor.
摘要翻译：非易失性存储器件包括电可编程晶体管和选择晶体管。选择晶体管连接在电子程序晶体管和可编程电压电源线之间。选择晶体管控制将编程电压供应线上的电压施加到电可编程晶体管。

4. 发明申请

US20080089136A1 NON-VOLATILE MEMORY DEVICE, METHOD OF MANUFACTURING THE SAME AND METHOD OF OPERATING THE SAME 失效
标题翻译：非易失性存储器件，其制造方法及其操作方法
公开(公告)号：US20080089136A1
公开(公告)日：2008-04-17
申请号：US11870762
申请日：2007-10-11
申请人： Hyun-Khe Yoo , Jeong-Uk Han , Hee-Seog Jeon , Sung-Gon Choi , Bo-Young Seo , Chang-Min Jeon , Ji-Do Ryu
发明人： Hyun-Khe Yoo , Jeong-Uk Han , Hee-Seog Jeon , Sung-Gon Choi , Bo-Young Seo , Chang-Min Jeon , Ji-Do Ryu
IPC分类号： G11C11/34 , H01L21/336 , H01L29/788
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A non-volatile memory device includes a first sensing line, a first word line, a depletion channel region, and impurity regions. The first sensing line and the first word line are formed adjacent to each other in parallel on a substrate. The first sensing line and the first word line have a tunnel oxide layer, a first conductive pattern, a dielectric layer pattern and a second conductive pattern sequentially stacked on the substrate. The depletion channel region is formed at an upper portion of the substrate under the first sensing line. The impurity regions are formed at upper portions of the substrate exposed by the first sensing line and the first word line.
摘要翻译：非易失性存储器件包括第一感测线，第一字线，耗尽沟道区和杂质区。第一感测线和第一字线在基板上彼此平行地相邻地形成。第一感测线和第一字线具有依次层叠在衬底上的隧道氧化物层，第一导电图案，电介质层图案和第二导电图案。耗尽沟道区形成在第一感测线下方的衬底的上部。在由第一感测线和第一字线露出的衬底的上部形成杂质区。

5. 发明申请

US20080008003A1 Non-Volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US20080008003A1
公开(公告)日：2008-01-10
申请号：US11789003
申请日：2007-04-23
申请人： Hyun-Khe Yoo , Ji-Do Ryu , Bo-Young Seo , Chang-Min Jeon , Hee-Seog Jeon , Sung-Gon Choi , Jeong-Uk Han
发明人： Hyun-Khe Yoo , Ji-Do Ryu , Bo-Young Seo , Chang-Min Jeon , Hee-Seog Jeon , Sung-Gon Choi , Jeong-Uk Han
IPC分类号： G11C11/34
CPC分类号： G11C16/0433 , G11C7/18 , G11C16/24 , G11C2207/002
摘要： A non-volatile memory device includes a memory cell block, a first switching block, and a second switching block. A plurality of memory cells are arranged in the memory cell block and each of the memory cells includes a memory transistor having a floating gate and a control gate and is connected to a local bit line and includes a selection transistor connected to the memory transistor in series that is connected to a source line. The first switching block selectively connects a global bit line to the local bit line and the second switching block controls the memory cells in the memory cell block in units of a predetermined number of bits. The first switching block includes at least two switching devices connected in parallel between the global bit line and the local bit line.
摘要翻译：非易失性存储器件包括存储器单元块，第一切换块和第二切换块。多个存储单元布置在存储单元块中，并且每个存储单元包括具有浮置栅极和控制栅极的存储晶体管，并连接到局部位线，并且包括串联连接到存储晶体管的选择晶体管它连接到源线。第一切换块选择性地将全局位线连接到本地位线，并且第二切换块以预定位数为单位来控制存储单元块中的存储单元。第一切换块包括在全局位线和局部位线之间并联连接的至少两个开关器件。

6. 发明授权

US07696561B2 Non-volatile memory device, method of manufacturing the same and method of operating the same 失效
标题翻译：非易失性存储器件，其制造方法及其操作方法
公开(公告)号：US07696561B2
公开(公告)日：2010-04-13
申请号：US11870762
申请日：2007-10-11
申请人： Hyun-Khe Yoo , Jeong-Uk Han , Hee-Seog Jeon , Sung-Gon Choi , Bo-Young Seo , Chang-Min Jeon , Ji-Do Ryu
发明人： Hyun-Khe Yoo , Jeong-Uk Han , Hee-Seog Jeon , Sung-Gon Choi , Bo-Young Seo , Chang-Min Jeon , Ji-Do Ryu
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A non-volatile memory device includes a first sensing line, a first word line, a depletion channel region, and impurity regions. The first sensing line and the first word line are formed adjacent to each other in parallel on a substrate. The first sensing line and the first word line have a tunnel oxide layer, a first conductive pattern, a dielectric layer pattern and a second conductive pattern sequentially stacked on the substrate. The depletion channel region is formed at an upper portion of the substrate under the first sensing line. The impurity regions are formed at upper portions of the substrate exposed by the first sensing line and the first word line.
摘要翻译：非易失性存储器件包括第一感测线，第一字线，耗尽沟道区和杂质区。第一感测线和第一字线在基板上彼此平行地相邻地形成。第一感测线和第一字线具有依次层叠在衬底上的隧道氧化物层，第一导电图案，电介质层图案和第二导电图案。耗尽沟道区形成在第一感测线下方的衬底的上部。在由第一感测线和第一字线露出的衬底的上部形成杂质区。

7. 发明授权

US07512003B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US07512003B2
公开(公告)日：2009-03-31
申请号：US11789003
申请日：2007-04-23
申请人： Hyun-Khe Yoo , Ji-Do Ryu , Bo-Young Seo , Chang-Min Jeon , Hee-Seog Jeon , Sung-Gon Choi , Jeong-Uk Han
发明人： Hyun-Khe Yoo , Ji-Do Ryu , Bo-Young Seo , Chang-Min Jeon , Hee-Seog Jeon , Sung-Gon Choi , Jeong-Uk Han
IPC分类号： G11C11/34
CPC分类号： G11C16/0433 , G11C7/18 , G11C16/24 , G11C2207/002
摘要： A non-volatile memory device includes a memory cell block, a first switching block, and a second switching block. A plurality of memory cells are arranged in the memory cell block and each of the memory cells includes a memory transistor having a floating gate and a control gate and is connected to a local bit line and includes a selection transistor connected to the memory transistor in series that is connected to a source line. The first switching block selectively connects a global bit line to the local bit line and the second switching block controls the memory cells in the memory cell block in units of a predetermined number of bits. The first switching block includes at least two switching devices connected in parallel between the global bit line and the local bit line.
摘要翻译：非易失性存储器件包括存储器单元块，第一切换块和第二切换块。多个存储单元布置在存储单元块中，并且每个存储单元包括具有浮置栅极和控制栅极的存储晶体管，并连接到局部位线，并且包括串联连接到存储晶体管的选择晶体管它连接到源线。第一切换块选择性地将全局位线连接到本地位线，而第二切换块以预定位数为单位来控制存储单元块中的存储单元。第一切换块包括在全局位线和局部位线之间并联连接的至少两个开关器件。

8. 发明授权

US07323740B2 Single chip data processing device with embedded nonvolatile memory and method thereof 失效
标题翻译：具有嵌入式非易失性存储器的单片数据处理装置及其方法
公开(公告)号：US07323740B2
公开(公告)日：2008-01-29
申请号：US10870166
申请日：2004-06-18
申请人： Weon-Ho Park , Sang-Soo Kim , Hyun-Khe Yoo , Sung-Chul Park , Byoung-Ho Kim , Ju-Ri Kim , Seung-Beom Yoon , Jeong-Uk Han
发明人： Weon-Ho Park , Sang-Soo Kim , Hyun-Khe Yoo , Sung-Chul Park , Byoung-Ho Kim , Ju-Ri Kim , Seung-Beom Yoon , Jeong-Uk Han
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L21/76224 , H01L21/823842 , H01L21/823857 , H01L21/823892 , H01L27/0922 , H01L27/105 , H01L27/11546
摘要： A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant concentration, and a nonvolatile memory cell formed on the second well. A device is described comprising four wells of various conductivity types with a nonvolatile memory cell formed on the second well. A device is described comprising a plurality of wells for isolating transistors of a plurality of voltage ranges, wherein each one of the plurality of wells contains at least one transistor of a particular voltage range, and wherein transistors of only one of the plurality of voltage ranges are within each of the plurality of wells. A method is described of isolating transistors of a first voltage range from transistors of another voltage range, comprising forming a first well to hold transistors only of a first particular voltage range, and forming a second well to hold transistors only of a second particular voltage range.
摘要翻译：描述了一种器件，其包括具有第一掺杂剂浓度的第一导电类型的衬底，在衬底中形成的第一阱，在衬底中形成并且比第一阱更深的第一导电类型的第二阱，第二阱具有比第一掺杂剂浓度高的掺杂剂浓度，以及形成在第二阱上的非易失性存储单元。描述了一种装置，其包括具有形成在第二阱上的非易失性存储单元的各种导电类型的四个阱。描述了一种器件，其包括用于隔离多个电压范围的晶体管的多个阱，其中多个阱中的每一个阱包含特定电压范围的至少一个晶体管，并且其中仅一个电压范围的晶体管在多个孔的每一个内。描述了一种将第一电压范围的晶体管与另一电压范围的晶体管隔离的方法，包括形成第一阱以仅保持第一特定电压范围的晶体管，以及形成第二阱以仅将晶体管保持在第二特定电压范围。

9. 发明申请

US20050162926A1 Split-gate type nonvolatile memory devices and methods for fabricating the same 审中-公开
标题翻译：分离式非易失性存储器件及其制造方法
公开(公告)号：US20050162926A1
公开(公告)日：2005-07-28
申请号：US11083305
申请日：2005-03-18
申请人： Hyun-Khe Yoo , Jeong-Uk Han
发明人： Hyun-Khe Yoo , Jeong-Uk Han
IPC分类号： H01L27/10 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115 , H01L27/11524
摘要： The nonvolatile memory device includes an electrically programmable transistor and a selection transistor. The selection transistor is connected between the electrically program transistor and a programmable voltage supply line. The selection transistor controls application of a voltage on the program voltage supply line to the electrically programmable transistor.
摘要翻译：非易失性存储器件包括电可编程晶体管和选择晶体管。选择晶体管连接在电子程序晶体管和可编程电压电源线之间。选择晶体管控制将编程电压供应线上的电压施加到电可编程晶体管。

10. 发明申请

US20070275509A1 Method of manufacturing NOR-type mask ROM device and semiconductor device including the same 失效
标题翻译：制造NOR型掩模ROM器件的方法和包括该器件的半导体器件
公开(公告)号：US20070275509A1
公开(公告)日：2007-11-29
申请号：US11882656
申请日：2007-08-03
申请人： Hyun-Khe Yoo , Weon-ho Park , Byoung-ho Kim
发明人： Hyun-Khe Yoo , Weon-ho Park , Byoung-ho Kim
IPC分类号： H01L21/8246
CPC分类号： H01L27/11266 , H01L21/823462 , H01L27/105 , H01L27/112 , H01L27/11293
摘要： A method of manufacturing a NOR-type mask ROM device includes forming a first gate electrode for an OFF cell and a second gate electrode for an ON cell on a semiconductor substrate of a first conductivity type. To code the mask ROM device, a plurality of source/drain regions is formed by implanting impurities of a second conductivity type, opposite the first conductivity type, into the semiconductor substrate adjacent only to one side of the first gate electrode and adjacent to both sides of the second gate electrode. To prevent misalignment of a bit line contact hole with a contact region, additional impurities are implanted only into a bit line contact region of the mask ROM device region. When a semiconductor device formed on the same substrate as the mask ROM device includes a double diffused region, additional implantation for both may be realized simultaneously.
摘要翻译：一种制造NOR型掩模ROM器件的方法包括在第一导电类型的半导体衬底上形成用于OFF电池的第一栅电极和用于ON电池的第二栅电极。为了对掩模ROM器件进行编码，通过将与第一导电类型相反的第二导电类型的杂质注入到仅与第一栅电极的一侧相邻并且邻近第二侧的半导体衬底中来形成多个源极/漏极区域的第二栅电极。为了防止与接触区域的位线接触孔不对准，仅将额外的杂质注入到掩模ROM器件区域的位线接触区域中。当形成在与掩模ROM器件相同的衬底上的半导体器件包括双扩散区域时，可以同时实现两者的附加注入。

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