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1. 发明申请

US20060124988A1 Methods of fabricating flash memory devices having self-aligned floating gate electrodes and related devices 审中-公开
标题翻译：制造具有自对准浮栅的闪存器件和相关器件的方法
公开(公告)号：US20060124988A1
公开(公告)日：2006-06-15
申请号：US11291142
申请日：2005-11-30
申请人： Sung-Hoi Hur , Jung-Dal Choi , Kyeong-Tae Kim , Jong-Ho Park , Jae-Duk Lee , Ki-Nam Kim
发明人： Sung-Hoi Hur , Jung-Dal Choi , Kyeong-Tae Kim , Jong-Ho Park , Jae-Duk Lee , Ki-Nam Kim
IPC分类号： H01L21/82 , H01L21/8238
CPC分类号： H01L27/115 , H01L27/11521
摘要： A semiconductor memory device is fabricated by forming an active region protruding from a semiconductor substrate, forming an isolation layer on the substrate adjacent opposing sidewalls of the active region, and forming a floating gate electrode on a surface of the active region between the opposing sidewalls thereof. The floating gate electrode is formed to extend beyond edges of the surface of the active region onto the isolation layer. A surface of the floating gate electrode adjacent the active region defines a plane, and the isolation layer is confined between the plane and the substrate. A control gate electrode is formed on a surface of the floating gate electrode opposite the active region. The control gate electrode may be formed to extend along sidewalls of the floating gate electrode towards the substrate beyond the plane defined by the surface of the floating gate electrode adjacent the active region. Related devices are also discussed.
摘要翻译：半导体存储器件通过形成从半导体衬底突出的有源区域形成，在邻近有源区域的相对侧壁的衬底上形成隔离层，以及在其相对侧壁之间的有源区域的表面上形成浮栅电极。浮栅电极被形成为延伸超过有源区表面的边缘到隔离层上。邻近有源区的浮栅电极的表面限定了一个平面，隔离层被限制在平面和衬底之间。控制栅电极形成在浮动栅电极的与有源区相对的表面上。控制栅电极可以被形成为沿着浮置栅电极的侧壁朝着衬底延伸超过由邻近有源区的浮栅的表面限定的平面。还讨论了相关设备。

2. 发明申请

US20130181278A1 NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE DEVICE 审中-公开
标题翻译：非易失性存储器件和用于制造器件的方法
公开(公告)号：US20130181278A1
公开(公告)日：2013-07-18
申请号：US13608796
申请日：2012-09-10
申请人： Sung-Hun LEE , Sung-Hoi Hur , Jong-Ho Park
发明人： Sung-Hun LEE , Sung-Hoi Hur , Jong-Ho Park
IPC分类号： H01L29/792
CPC分类号： H01L27/1157 , H01L21/764 , H01L27/11524 , H01L29/40114 , H01L29/40117 , H01L29/42324 , H01L29/4234
摘要： Provided is a non-volatile memory device that includes a substrate including a plurality of active regions extending in a first direction and a plurality of element isolation trenches disposed between the active regions, a plurality of tunnel insulating layer patterns and a plurality of storage layer patterns sequentially disposed on the substrate, a plurality of blocking insulating layers and a plurality of gate electrodes disposed on the storage layer patterns and extending in a second direction perpendicular to the first direction, and first insulating layers including air gaps disposed between the active regions on the element isolation trenches and extending in the first direction, wherein the active regions include first active regions and second active regions adjacent to the first active regions, wherein a width of first air gaps is different from a width of second air gaps.
摘要翻译：提供了一种非易失性存储器件，其包括：衬底，其包括在第一方向上延伸的多个有源区和设置在有源区之间的多个元件隔离沟槽;多个隧道绝缘层图案和多个存储层图案顺序地设置在基板上，多个阻挡绝缘层和多个栅电极，其设置在存储层图案上并沿垂直于第一方向的第二方向延伸，并且第一绝缘层包括设置在第一方向上的有源区之间的气隙元件隔离沟槽并沿第一方向延伸，其中有源区包括与第一有源区相邻的第一有源区和第二有源区，其中第一气隙的宽度不同于第二气隙的宽度。

3. 发明授权

US07592665B2 Non-volatile memory devices having floating gates 失效
标题翻译：具有浮动门的非易失性存储器件
公开(公告)号：US07592665B2
公开(公告)日：2009-09-22
申请号：US11594327
申请日：2006-11-08
申请人： Joon-Hee Lee , Jong-Ho Park , Jin-Hyun Shin , Sung-Hoi Hur , Yong-Seok Kim , Jong-Won Kim
发明人： Joon-Hee Lee , Jong-Ho Park , Jin-Hyun Shin , Sung-Hoi Hur , Yong-Seok Kim , Jong-Won Kim
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A nonvolatile memory device may include a substrate having a cell region, and a cell device isolation layer on the cell region of the substrate to define a cell active region. A floating gate may include a lower floating gate and an upper floating gate sequentially stacked on the cell active region, and a tunnel insulation pattern may be between the floating gate and the cell active region. A control gate electrode may be on the floating gate, and a blocking insulation pattern may be between the control gate electrode and the floating gate. More particularly, the upper floating gate may include a flat portion on the lower floating gate and a pair of wall portions extending upward from both edges of the flat portion adjacent to the cell device isolation layer. Moreover, a width of an upper portion of a space surrounded by the flat portion and the pair of wall portions may be larger than a width of a lower portion of the space. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括具有单元区域的衬底和在衬底的单元区域上的单元器件隔离层，以限定电池活性区域。浮置栅极可以包括顺序堆叠在单元有源区上的下浮置栅极和上浮置栅极，并且隧道绝缘图案可以在浮栅和电池有源区之间。控制栅极电极可以在浮置栅极上，并且阻挡绝缘图案可以在控制栅电极和浮栅之间。更具体地说，上部浮动栅极可以包括在下部浮动栅极上的平坦部分和从邻近电池器件隔离层的平坦部分的两个边缘向上延伸的一对壁部分。此外，由平坦部分和一对壁部分围绕的空间的上部的宽度可以大于空间的下部的宽度。还讨论了相关方法。

4. 发明申请

US20110101439A1 INTERCONNECTION STRUCTURES FOR SEMICONDCUTOR DEVICES 审中-公开
标题翻译：用于半导体器件的互连结构
公开(公告)号：US20110101439A1
公开(公告)日：2011-05-05
申请号：US12987440
申请日：2011-01-10
申请人： Jin-Taek Park , Jong-Ho Park , Sung-Hoi Hur , Hyun-Suk Kim
发明人： Jin-Taek Park , Jong-Ho Park , Sung-Hoi Hur , Hyun-Suk Kim
IPC分类号： H01L29/78
CPC分类号： H01L21/76895 , H01L21/76877 , H01L23/485
摘要： An interconnection structure for a semiconductor device includes an inter-level insulation layer disposed on a semiconductor substrate. First contact constructions penetrate the inter-level insulation layer. Second contact constructions penetrate the inter-level insulation layer. Metal interconnections connect the first contact constructions to the second contact constructions on the inter-level insulation layer. The first contact constructions include first and second plugs stacked in sequence and the second contact constructions include the second plug.
摘要翻译：半导体器件的互连结构包括设置在半导体衬底上的级间绝缘层。第一接触结构穿透层间绝缘层。第二接触构造穿透层间绝缘层。金属互连将第一接触结构连接到层间绝缘层上的第二接触结构。第一接触构造包括依次堆叠的第一和第二插塞，并且第二接触构造包括第二插塞。

5. 发明授权

US07871921B2 Methods of forming interconnection structures for semiconductor devices 有权
标题翻译：形成半导体器件互连结构的方法
公开(公告)号：US07871921B2
公开(公告)日：2011-01-18
申请号：US11022240
申请日：2004-12-22
申请人： Jin-Taek Park , Jong-Ho Park , Sung-Hoi Hur , Hyun-Suk Kim
发明人： Jin-Taek Park , Jong-Ho Park , Sung-Hoi Hur , Hyun-Suk Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76895 , H01L21/76877 , H01L23/485
摘要： An interconnection structure for a semiconductor device includes an inter-level insulation layer disposed on a semiconductor substrate. First contact constructions penetrate the inter-level insulation layer. Second contact constructions penetrate the inter-level insulation layer. Metal interconnections connect the first contact constructions to the second contact constructions on the inter-level insulation layer. The first contact constructions include first and second plugs stacked in sequence and the second contact constructions include the second plug.
摘要翻译：半导体器件的互连结构包括设置在半导体衬底上的级间绝缘层。第一接触结构穿透层间绝缘层。第二接触构造穿透层间绝缘层。金属互连将第一接触结构连接到层间绝缘层上的第二接触结构。第一接触构造包括依次堆叠的第一和第二插塞，并且第二接触构造包括第二插塞。

6. 发明申请

US20070108498A1 Non-volatile memory devices having floating gates and related methods of forming the same 失效
标题翻译：具有浮动栅极的非易失性存储器件及其相关方法
公开(公告)号：US20070108498A1
公开(公告)日：2007-05-17
申请号：US11594327
申请日：2006-11-08
申请人： Joon-Hee Lee , Jong-Ho Park , Jin-Hyun Shin , Sung-Hoi Hur , Yong-Seok Kim , Jong-Won Kim
发明人： Joon-Hee Lee , Jong-Ho Park , Jin-Hyun Shin , Sung-Hoi Hur , Yong-Seok Kim , Jong-Won Kim
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A nonvolatile memory device may include a substrate having a cell region, and a cell device isolation layer on the cell region of the substrate to define a cell active region. A floating gate may include a lower floating gate and an upper floating gate sequentially stacked on the cell active region, and a tunnel insulation pattern may be between the floating gate and the cell active region. A control gate electrode may be on the floating gate, and a blocking insulation pattern may be between the control gate electrode and the floating gate. More particularly, the upper floating gate may include a flat portion on the lower floating gate and a pair of wall portions extending upward from both edges of the flat portion adjacent to the cell device isolation layer. Moreover, a width of an upper portion of a space surrounded by the flat portion and the pair of wall portions may be larger than a width of a lower portion of the space. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括具有单元区域的衬底和在衬底的单元区域上的单元器件隔离层，以限定电池活性区域。浮置栅极可以包括顺序堆叠在单元有源区上的下浮置栅极和上浮置栅极，并且隧道绝缘图案可以在浮栅和电池有源区之间。控制栅极电极可以在浮置栅极上，并且阻挡绝缘图案可以在控制栅电极和浮栅之间。更具体地说，上部浮动栅极可以包括在下部浮动栅极上的平坦部分和从邻近电池器件隔离层的平坦部分的两个边缘向上延伸的一对壁部分。此外，由平坦部分和一对壁部分围绕的空间的上部的宽度可以大于空间的下部的宽度。还讨论了相关方法。

7. 发明申请

US20050250307A1 Interconnection structures for semicondcutor devices and methods of forming the same 有权
标题翻译：半连接装置的互连结构及其形成方法
公开(公告)号：US20050250307A1
公开(公告)日：2005-11-10
申请号：US11022240
申请日：2004-12-22
申请人： Jin-Taek Park , Jong-Ho Park , Sung-Hoi Hur , Hyun-Suk Kim
发明人： Jin-Taek Park , Jong-Ho Park , Sung-Hoi Hur , Hyun-Suk Kim
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76895 , H01L21/76877 , H01L23/485
摘要： An interconnection structure for a semiconductor device includes an inter-level insulation layer disposed on a semiconductor substrate. First contact constructions penetrate the inter-level insulation layer. Second contact constructions penetrate the inter-level insulation layer. Metal interconnections connect the first contact constructions to the second contact constructions on the inter-level insulation layer. The first contact constructions include first and second plugs stacked in sequence and the second contact constructions include the second plug.
摘要翻译：半导体器件的互连结构包括设置在半导体衬底上的级间绝缘层。第一接触结构穿透层间绝缘层。第二接触构造穿透层间绝缘层。金属互连将第一接触结构连接到层间绝缘层上的第二接触结构。第一接触构造包括依次堆叠的第一和第二插塞，并且第二接触构造包括第二插塞。

8. 发明申请

US20070090437A1 SEMICONDUCTOR DEVICES INCLUDING GATE PATTERNS FOR REDUCING VOID FORMATION 审中-公开
标题翻译：半导体器件，包括用于减少失调形成的栅格图案
公开(公告)号：US20070090437A1
公开(公告)日：2007-04-26
申请号：US11613468
申请日：2006-12-20
申请人： Jong-Won Kim , Jong-Ho Park , Jung-Dal Choi
发明人： Jong-Won Kim , Jong-Ho Park , Jung-Dal Choi
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method of forming a semiconductor device includes forming an insulating layer on a semiconductor substrate. The insulating layer has a trench therein with opposing sidewalls and a bottom surface. A first conductive layer is formed on the sidewalls and on the bottom surface of the trench to define a gap region. A portion of the first conductive layer is removed to thereby increase a width of the gap region. The first conductive layer may be removed from the sidewalls and the bottom surface of the trench such that an upper width of the gap region is greater than or equal to a lower width of the gap region. A second conductive layer is formed in the gap region after removing the portion of the first conductive layer to fill the gap region.
摘要翻译：形成半导体器件的方法包括在半导体衬底上形成绝缘层。绝缘层在其中具有相对的侧壁和底面的沟槽。第一导电层形成在沟槽的侧壁和底表面上以限定间隙区域。去除第一导电层的一部分，从而增加间隙区域的宽度。可以从沟槽的侧壁和底表面去除第一导电层，使得间隙区域的上部宽度大于或等于间隙区域的较低宽度。在去除第一导电层的部分以填充间隙区域之后，在间隙区域中形成第二导电层。

9. 发明授权

US07273783B2 Methods for reducing void formation in semiconductor devices 失效
标题翻译：减少半导体器件中空隙形成的方法
公开(公告)号：US07273783B2
公开(公告)日：2007-09-25
申请号：US11018778
申请日：2004-12-21
申请人： Jong-Won Kim , Jong-Ho Park , Jung-Dal Choi
发明人： Jong-Won Kim , Jong-Ho Park , Jung-Dal Choi
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method of forming a semiconductor device includes forming an insulating layer on a semiconductor substrate. The insulating layer has a trench therein with opposing sidewalls and a bottom surface. A first conductive layer is formed on the sidewalls and on the bottom surface of the trench to define a gap region. A portion of the first conductive layer is removed to thereby increase a width of the gap region. The first conductive layer may be removed from the sidewalls and the bottom surface of the trench such that an upper width of the gap region is greater than or equal to a lower width of the gap region. A second conductive layer is formed in the gap region after removing the portion of the first conductive layer to fill the gap region.
摘要翻译：形成半导体器件的方法包括在半导体衬底上形成绝缘层。绝缘层在其中具有相对的侧壁和底面的沟槽。第一导电层形成在沟槽的侧壁和底表面上以限定间隙区域。去除第一导电层的一部分，从而增加间隙区域的宽度。可以从沟槽的侧壁和底表面去除第一导电层，使得间隙区域的上部宽度大于或等于间隙区域的较低宽度。在去除第一导电层的部分以填充间隙区域之后，在间隙区域中形成第二导电层。

10. 发明申请

US20060030137A1 Methods for reducing void formation in semiconductor devices and related devices 失效
标题翻译：减少半导体器件和相关器件中空隙形成的方法
公开(公告)号：US20060030137A1
公开(公告)日：2006-02-09
申请号：US11018778
申请日：2004-12-21
申请人： Jong-Won Kim , Jong-Ho Park , Jung-Dal Choi
发明人： Jong-Won Kim , Jong-Ho Park , Jung-Dal Choi
IPC分类号： H01L21/76
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method of forming a semiconductor device includes forming an insulating layer on a semiconductor substrate. The insulating layer has a trench therein with opposing sidewalls and a bottom surface. A first conductive layer is formed on the sidewalls and on the bottom surface of the trench to define a gap region. A portion of the first conductive layer is removed to thereby increase a width of the gap region. The first conductive layer may be removed from the sidewalls and the bottom surface of the trench such that an upper width of the gap region is greater than or equal to a lower width of the gap region. A second conductive layer is formed in the gap region after removing the portion of the first conductive layer to fill the gap region.
摘要翻译：形成半导体器件的方法包括在半导体衬底上形成绝缘层。绝缘层在其中具有相对的侧壁和底面的沟槽。第一导电层形成在沟槽的侧壁和底表面上以限定间隙区域。去除第一导电层的一部分，从而增加间隙区域的宽度。可以从沟槽的侧壁和底表面去除第一导电层，使得间隙区域的上部宽度大于或等于间隙区域的较低宽度。在去除第一导电层的部分以填充间隙区域之后，在间隙区域中形成第二导电层。

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