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1. 发明授权

US08400860B2 Electrical fuse memory 有权
标题翻译：电熔丝记忆体
公开(公告)号：US08400860B2
公开(公告)日：2013-03-19
申请号：US12839542
申请日：2010-07-20
申请人： Sung-Chieh Lin , David Yen , Wei-Li Liao , Jiann-Tseng Huang , Kuoyuan (Peter) Hsu
发明人： Sung-Chieh Lin , David Yen , Wei-Li Liao , Jiann-Tseng Huang , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/16
CPC分类号： G11C17/16
摘要： Some embodiments regard a memory array that has a plurality of rows and columns. A column includes a program control device, a plurality of eFuse memory cells in the column, a sense amplifier, and a bit line coupling the program control device, the plurality of memory cells in the column, and the sense amplifier. A row includes a plurality of eFuse memory cells in the row, a word line coupling the plurality of eFuse memory cells in the row, and a footer configured as a current path for the plurality of eFuse memory cells in the row.
摘要翻译：一些实施例涉及具有多个行和列的存储器阵列。列包括程序控制装置，列中的多个eFuse存储器单元，读出放大器和耦合程序控制装置，列中的多个存储单元和读出放大器的位线。行包括行中的多个eFuse存储器单元，耦合行中的多个eFuse存储器单元的字线和被配置为行中的多个eFuse存储器单元的当前路径的页脚。

2. 发明授权

US08760955B2 Electrical fuse memory arrays 有权
标题翻译：电熔丝存储器阵列
公开(公告)号：US08760955B2
公开(公告)日：2014-06-24
申请号：US13278686
申请日：2011-10-21
申请人： Wei-Li Liao , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： Wei-Li Liao , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/16
CPC分类号： G11C17/16 , G11C17/18
摘要： A mechanism of reconfiguring an eFuse memory array to have two or more neighboring eFuse bit cells placed side by and side and sharing a program bit line. By allowing two or more neighboring eFuse bit cells to share a program bit line, the length of the program bit line is shortened, which results in lower resistivity of the program bit line. The width of the program bit line may also be increased to further reduce the resistivity of program bit line. Program bit lines with low resistance and high current are needed for advanced eFuse memory arrays using low-resistivity eFuses.
摘要翻译：重新配置eFuse存储器阵列以使两个或更多个相邻的eFuse位单元被放置在旁边并共享一个程序位线的机制。通过允许两个或多个相邻的eFuse位单元共享程序位线，程序位线的长度被缩短，这导致程序位线的电阻较低。也可以增加编程位线的宽度，以进一步降低程序位线的电阻率。使用低电阻率eFuse的高级eFuse存储器阵列需要具有低电阻和高电流的程序位线。

3. 发明授权

US08614927B2 Current leakage reduction 有权
标题翻译：电流泄漏减少
公开(公告)号：US08614927B2
公开(公告)日：2013-12-24
申请号：US13595551
申请日：2012-08-27
申请人： Sung-Chieh Lin , Kuoyuan (Peter) Hsu , Jiann-Tseng Huang , Wei-Li Liao
发明人： Sung-Chieh Lin , Kuoyuan (Peter) Hsu , Jiann-Tseng Huang , Wei-Li Liao
IPC分类号： G11C7/00
CPC分类号： G11C8/12 , G11C17/18
摘要： This description relates to a circuit including a bit line. The circuit further includes at least one memory bank. The at least one memory bank includes at least one memory cell, a first device configured to provide a current path between the bit line and the at least one memory cell when the at least one memory cell is activated, and a second device configured to reduce current leakage between the bit line and the at least one memory cell when the at least one memory cell is deactivated. The circuit further includes a tracking device configured to receive a mirror current substantially equal to a current along the current path, the tracking device configured to have a resistance substantially equal to a cumulative resistance of all memory cells of the at least one memory cell.
摘要翻译：本说明书涉及包括位线的电路。电路还包括至少一个存储体。所述至少一个存储体包括至少一个存储单元，配置为当所述至少一个存储单元被激活时在所述位线和所述至少一个存储器单元之间提供电流路径的第一设备，以及被配置为减少当所述至少一个存储器单元被停用时，所述位线与所述至少一个存储器单元之间的电流泄漏。电路还包括跟踪装置，其被配置为接收基本上等于沿着电流路径的电流的反射镜电流，跟踪装置被配置为具有基本上等于至少一个存储器单元的所有存储器单元的累积电阻的电阻。

4. 发明授权

US08847350B2 Metal-via fuse 有权
标题翻译：金属通孔保险丝
公开(公告)号：US08847350B2
公开(公告)日：2014-09-30
申请号：US13599654
申请日：2012-08-30
申请人： Sung-Chieh Lin , Kuoyuan (Peter) Hsu , Wei-Li Liao , Yun-Han Chen , Chen-Ming Hung
发明人： Sung-Chieh Lin , Kuoyuan (Peter) Hsu , Wei-Li Liao , Yun-Han Chen , Chen-Ming Hung
IPC分类号： H01L23/52
CPC分类号： H01L23/5256 , H01L23/522 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a metal-via fuse. The metal-via fuse and a programming transistor form a one-time programmable (OTP) memory cell. The metal-via fuse has a high resistance and can be programmed with a low programming voltage, which expands the programming window.
摘要翻译：本文公开的方法和结构的实施例提供了形成和编程金属通孔保险丝的机制。金属通孔保险丝和编程晶体管形成一次性可编程（OTP）存储单元。金属通路保险丝具有高电阻，并且可以用低编程电压进行编程，从而扩展编程窗口。

5. 发明授权

US08482952B2 One time programming bit cell 有权
标题翻译：一次编程位单元格
公开(公告)号：US08482952B2
公开(公告)日：2013-07-09
申请号：US13029552
申请日：2011-02-17
申请人： Sung-Chieh Lin , Wei-Li Liao , Kuoyuan (Peter) Hsu
发明人： Sung-Chieh Lin , Wei-Li Liao , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18
摘要： A one time programming (OTP) memory cell includes a first transistor and a second transistor. The first transistor has a first drain, a first source, a first gate, and a first normal operational voltage value higher that a second normal operational voltage value of the second transistor. The second transistor has a second drain, a second source, and a second gate. The first source is coupled to the second drain. The second source is configured to detect data stored in the OTP memory cell.
摘要翻译：一次编程（OTP）存储单元包括第一晶体管和第二晶体管。第一晶体管具有比第二晶体管的第二正常工作电压值更高的第一漏极，第一源极，第一栅极和第一正常工作电压值。第二晶体管具有第二漏极，第二源极和第二栅极。第一源耦合到第二漏极。第二个源被配置为检测存储在OTP存储单元中的数据。

6. 发明授权

US08824234B2 Electrical fuse memory 有权
标题翻译：电熔丝记忆体
公开(公告)号：US08824234B2
公开(公告)日：2014-09-02
申请号：US13771674
申请日：2013-02-20
申请人： Sung-Chieh Lin , David Yen , Wei-Li Liao , Jiann-Tseng Huang , Kuoyuan (Peter) Hsu
发明人： Sung-Chieh Lin , David Yen , Wei-Li Liao , Jiann-Tseng Huang , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/16
CPC分类号： G11C17/16
摘要： A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on.
摘要翻译：读取eFuse存储单元列中的eFuse的方法包括将eFuse的第一端与第一电路断开。 eFuse的第二端和节点之间的第二电路被激活以绕过第三电路，其中第三电路包括在eFuse的第二端和节点之间的二极管器件。与节点耦合的页脚被打开。

7. 发明授权

US08787109B2 Word line driver having a control switch 有权
标题翻译：具有控制开关的字线驱动器
公开(公告)号：US08787109B2
公开(公告)日：2014-07-22
申请号：US13466518
申请日：2012-05-08
申请人： Wei-Li Liao , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： Wei-Li Liao , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： G11C8/00 , G11C5/14 , G11C16/06
CPC分类号： G11C8/08
摘要： A word line driver including a control switch configured to receive a control signal, where the control switch is between a first node configured to receive an operating voltage signal and a second node configured to determine an output of the word line driver. The word line driver further includes a cross-coupled amplifier electrically connected to the second node. The word line driver further includes at least one inverter electrically connected to the cross-coupled amplifier. A semiconductor device including the word line driver and a memory array including at least one electronic fuse.
摘要翻译：一种字线驱动器，包括被配置为接收控制信号的控制开关，其中所述控制开关位于被配置为接收工作电压信号的第一节点和被配置为确定所述字线驱动器的输出的第二节点之间。字线驱动器还包括电连接到第二节点的交叉耦合放大器。字线驱动器还包括电连接到交叉耦合放大器的至少一个反相器。包括字线驱动器和包括至少一个电子熔丝的存储器阵列的半导体器件。

8. 发明授权

US08542549B2 Electrical fuse bit cell 有权
标题翻译：电熔丝位元
公开(公告)号：US08542549B2
公开(公告)日：2013-09-24
申请号：US13205009
申请日：2011-08-08
申请人： Sung-Chieh Lin , Wei-Li Liao , Kuoyuan (Peter) Hsu
发明人： Sung-Chieh Lin , Wei-Li Liao , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/18
CPC分类号： G11C17/16 , G11C17/18
摘要： An electrical fuse (eFuse) bit cell includes a program transistor, a read transistor, and an eFuse. The program transistor has a first program terminal, a second program terminal, and a third program terminal. The read transistor has a first read terminal, a second read terminal, and a third read terminal. The eFuse has a first end and a second end. The first end, the first program terminal, and the second read terminal are coupled together. The read transistor is configured to be off and the program transistor is configured to be on when the eFuse bit cell is in a program mode. The program transistor is configured to be off and the read transistor is configured to be on when the eFuse bit cell is in a read mode.
摘要翻译：电熔丝（eFuse）位单元包括程序晶体管，读晶体管和eFuse。程序晶体管具有第一程序终端，第二程序终端和第三程序终端。读取晶体管具有第一读取端子，第二读取端子和第三读取端子。 eFuse具有第一端和第二端。第一端，第一程序终端和第二读终端耦合在一起。读晶体管被配置为截止，并且当eFuse位单元处于编程模式时，程序晶体管被配置为导通。程序晶体管被配置为截止，并且当eFuse位单元处于读取模式时，读取晶体管被配置为导通。

9. 发明授权

US08194490B2 Electrical fuse memory arrays 有权
标题翻译：电熔丝存储器阵列
公开(公告)号：US08194490B2
公开(公告)日：2012-06-05
申请号：US12877646
申请日：2010-09-08
申请人： Po-Hung Chen , Chin-Huang Wang , Yen-Chieh Huang , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： Po-Hung Chen , Chin-Huang Wang , Yen-Chieh Huang , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/18
CPC分类号： G11C17/165
摘要： Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column.
摘要翻译：一些实施例涉及具有以行和列，多个位线和多个字线布置的多个eFuse存储器单元的存储器阵列。列包括位线选择器，耦合到位线选择器的位线和多个eFuse存储器单元。该列的eFuse存储单元包括PMOS晶体管和eFuse。 PMOS晶体管的漏极耦合到eFuse的第一端。 PMOS晶体管的栅极耦合到字线。 PMOS晶体管的源极耦合到列的位线。

10. 发明授权

US08946825B2 Integrated circuit structure to resolve deep-well plasma charging problem and method of forming the same 有权
标题翻译：集成电路结构解决深井等离子体充电问题及其形成方法
公开(公告)号：US08946825B2
公开(公告)日：2015-02-03
申请号：US13433194
申请日：2012-03-28
申请人： David Yen , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： David Yen , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： H01L23/62
CPC分类号： H01L27/0928 , H01L21/263 , H01L21/823871 , H01L21/823878 , H01L21/823892 , H01L27/0629 , H01L29/6609
摘要： During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW.
摘要翻译：在各种处理操作期间，来自工艺等离子体的离子可以转移到在器件结构下形成的深n阱（DNW）。反向偏置二极管可以连接到信号线以保护形成在DNW外部的栅极电介质，并且连接到形成在DNW内部的晶体管的漏极。

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