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1. 发明授权

US08847350B2 Metal-via fuse 有权
标题翻译：金属通孔保险丝
公开(公告)号：US08847350B2
公开(公告)日：2014-09-30
申请号：US13599654
申请日：2012-08-30
申请人： Sung-Chieh Lin , Kuoyuan (Peter) Hsu , Wei-Li Liao , Yun-Han Chen , Chen-Ming Hung
发明人： Sung-Chieh Lin , Kuoyuan (Peter) Hsu , Wei-Li Liao , Yun-Han Chen , Chen-Ming Hung
IPC分类号： H01L23/52
CPC分类号： H01L23/5256 , H01L23/522 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a metal-via fuse. The metal-via fuse and a programming transistor form a one-time programmable (OTP) memory cell. The metal-via fuse has a high resistance and can be programmed with a low programming voltage, which expands the programming window.
摘要翻译：本文公开的方法和结构的实施例提供了形成和编程金属通孔保险丝的机制。金属通孔保险丝和编程晶体管形成一次性可编程（OTP）存储单元。金属通路保险丝具有高电阻，并且可以用低编程电压进行编程，从而扩展编程窗口。

2. 发明授权

US09135099B2 Memory error correction 有权
标题翻译：内存纠错
公开(公告)号：US09135099B2
公开(公告)日：2015-09-15
申请号：US13434588
申请日：2012-03-29
申请人： Yun-Han Chen , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： Yun-Han Chen , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： G11C29/00 , G06F11/07 , G06F11/10 , H03M13/19 , H03M13/00
CPC分类号： G06F11/073 , G06F11/0793 , G06F11/1008 , H03M13/19 , H03M13/6561
摘要： A method includes, by a first circuit, converting a plurality of bits in a first format to a second format. The plurality of bits in the second format is used, by a second circuit, to program a plurality of memory cells corresponding to the plurality of bits. The first format is a parallel format. The second format is a serial format. The first circuit and the second circuit are electrically coupled together in a chip. In some embodiments, the plurality of bits includes address information, cell data information, and program information of a memory cell that has an error. In some embodiments, the plurality of bits includes word data information of a word and error code and correction information corresponding to the word data information of the word.
摘要翻译：一种方法包括通过第一电路将第一格式的多个比特转换成第二格式。通过第二电路使用第二格式的多个比特来对与多个比特相对应的多个存储单元进行编程。第一种格式是并行格式。第二种格式是串行格式。第一电路和第二电路在芯片中电耦合在一起。在一些实施例中，多个位包括地址信息，单元数据信息和具有错误的存储器单元的程序信息。在一些实施例中，多个比特包括单词的字数据信息和与单词的单词数据信息对应的错误代码和校正信息。

3. 发明授权

US07800231B2 Ball grid array package and substrate within 有权
标题翻译：球栅阵列封装和衬底内
公开(公告)号：US07800231B2
公开(公告)日：2010-09-21
申请号：US11453804
申请日：2006-06-16
申请人： Yun-Han Chen
发明人： Yun-Han Chen
IPC分类号： H01L21/00
CPC分类号： H01L23/49816 , H01L23/49838 , H01L23/50 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A ball grid array (BGA) package includes a substrate and a chip. A bottom surface of the substrate includes a central area and a marginal area. Several source balls are disposed in the central area. Several ball groups are disposed in the marginal area. Each ball group includes one ground ball and at most three signal balls. The chip is disposed on a top surface of the substrate and electrically connected to the substrate.
摘要翻译：球栅阵列（BGA）封装包括衬底和芯片。基板的底面包括中心区域和边缘区域。几个源球设置在中心区域。边缘地带有几个球组。每个球组包括一个地球和至多三个信号球。芯片设置在基板的顶表面上并与基板电连接。

4. 发明申请

US20140359311A1 Controlling Power Delivery To A Processor Via A Bypass 有权
标题翻译：通过旁路控制处理器的电力输送
公开(公告)号：US20140359311A1
公开(公告)日：2014-12-04
申请号：US13906652
申请日：2013-05-31
申请人： Sanjeev S. Jahagirdar , Satish K. Damaraju , Yun-Han Chen , Ryan D. Wells , Inder M. Sodhi , Vishram Sarurkar , Ken Drottar , Ashish V. Choubal , Rabiul Islam
发明人： Sanjeev S. Jahagirdar , Satish K. Damaraju , Yun-Han Chen , Ryan D. Wells , Inder M. Sodhi , Vishram Sarurkar , Ken Drottar , Ashish V. Choubal , Rabiul Islam
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/3243 , G06F1/3296 , G06F9/5094 , Y02D10/152 , Y02D10/172 , Y02D10/22
摘要： In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括多个域，每个域以独立可控的电压和频率工作，多个线性稳压器各自接收来自芯片外源的第一电压并可控制以将调节电压提供给至少一个以及多个选择器，每个选择器都耦合到所述域中的一个，其中每个选择器被配置为从所述线性调节器之一提供调节电压或将旁路电压提供给相应的域。描述和要求保护其他实施例。

5. 发明申请

US20070018319A1 Ball grid array package and substrate within 有权
标题翻译：球栅阵列封装和衬底内
公开(公告)号：US20070018319A1
公开(公告)日：2007-01-25
申请号：US11453804
申请日：2006-06-16
申请人： Yun-Han Chen
发明人： Yun-Han Chen
IPC分类号： H01L23/48
CPC分类号： H01L23/49816 , H01L23/49838 , H01L23/50 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A ball grid array (BGA) package includes a substrate and a chip. A bottom surface of the substrate includes a central area and a marginal area. Several source balls are disposed in the central area. Several ball groups are disposed in the marginal area. Each ball group includes one ground ball and at most three signal balls. The chip is disposed on a top surface of the substrate and electrically connected to the substrate.
摘要翻译：球栅阵列（BGA）封装包括衬底和芯片。基板的底面包括中心区域和边缘区域。几个源球设置在中心区域。边缘地带有几个球组。每个球组包括一个地球和至多三个信号球。芯片设置在基板的顶表面上并与基板电连接。

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