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1. 发明申请

US20140242530A1 SUBSTRATE HEAT TREATMENT APPARATUS AND METHOD 审中-公开
标题翻译：基板热处理装置和方法
公开(公告)号：US20140242530A1
公开(公告)日：2014-08-28
申请号：US13945324
申请日：2013-07-18
申请人： Sung Guk An , Jun Heo , Jong Hyun Yun , Kyoung Wan Park , Ho Young Kang , Byung Il Lee
发明人： Sung Guk An , Jun Heo , Jong Hyun Yun , Kyoung Wan Park , Ho Young Kang , Byung Il Lee
IPC分类号： H01L21/02
CPC分类号： H01L21/324 , F27B17/0025 , H01L21/67109 , H01L21/67115
摘要： Substrate heat treatment apparatus and method are provided. According to an embodiment of the present invention, there is provided a substrate heat treatment apparatus including an inner shell configured to form a substrate housing space to house at least one substrate, an outer shell configured to cover the inner shell, and having at least one gas hole, and at least one heater configured to heat the substrate, wherein the at least one gas hole is configured to allow a first gas to be injected into a space between the inner shell and the outer shell.
摘要翻译：提供基板热处理装置和方法。根据本发明的实施例，提供了一种基板热处理设备，其包括：内壳，其构造成形成用于容纳至少一个基板的基板容纳空间;外壳，构造成覆盖所述内壳，并且具有至少一个气体孔和至少一个加热构造成加热基底的加热器，其中所述至少一个气孔被配置为允许第一气体被注入到所述内壳和所述外壳之间的空间中。

2. 发明授权

US06797629B2 Method of manufacturing nano transistors 失效
标题翻译：制造纳米晶体管的方法
公开(公告)号：US06797629B2
公开(公告)日：2004-09-28
申请号：US10185104
申请日：2002-06-27
申请人： Moon Gyu Jang , Won Ju Cho , Seong Jae Lee , Kyoung Wan Park
发明人： Moon Gyu Jang , Won Ju Cho , Seong Jae Lee , Kyoung Wan Park
IPC分类号： H01L21302
CPC分类号： H01L29/78648 , H01L21/84 , H01L27/1203 , H01L29/78654
摘要： The present invention relates to a method of manufacturing a nano transistor. The present invention manufactures the nano transistor without changing a conventional method of forming the nano transistor formed on a SOI substrate. Further, the present invention includes forming a N well and a P well at giving regions of an underlying silicon substrate so that a given voltage can be individually applied to a NMOS transistor and a PMOS transistor. Therefore, the present invention can control the threshold voltage to prevent an increase of the leakage current.
摘要翻译：本发明涉及纳米晶体管的制造方法。本发明制造纳米晶体管而不改变形成在SOI衬底上的纳米晶体管的常规方法。此外，本发明包括在给定下面的硅衬底的区域上形成N阱和P阱，使得可以将给定的电压单独地施加到NMOS晶体管和PMOS晶体管。因此，本发明可以控制阈值电压以防止漏电流的增加。

3. 发明授权

US06323504B1 Single-electron memory device using an electron-hole coulomb blockade 失效
标题翻译：使用电子孔库仑封锁的单电子存储器件
公开(公告)号：US06323504B1
公开(公告)日：2001-11-27
申请号：US09495740
申请日：2000-02-01
申请人： Min Cheol Shin , Seong Jae Lee , Kyoung Wan Park
发明人： Min Cheol Shin , Seong Jae Lee , Kyoung Wan Park
IPC分类号： H01L2906
CPC分类号： B82Y10/00 , G11C2216/08 , H01L29/7888 , Y10S977/937
摘要： A single-electron memory device using the electron-hole Coulomb blockade is provided. A single-electron memory device in accordance with an embodiment of the present invention includes a plurality of quantum dot tunnel-junction arrays, a gate electrode, and source and drain electrodes. The plurality of quantum dot tunnel-junction arrays include at least two tunnel-junctions, are parallelly coupled to each other, and are well separated from each other to prevent single-electron tunneling between them. One of the plurality of quantum dot tunnel-junction arrays includes the gate electrode, and the voltage applied to the gate electrode can vary the number of electron-hole pairs. Each of the above-mentioned plurality of quantum dot tunnel-junction arrays includes separate source and drain electrodes where voltages are applied
摘要翻译：提供了使用电子孔库仑封锁的单电子存储器件。根据本发明的实施例的单电子存储器件包括多个量子点隧道结阵列，栅电极和源电极和漏电极。多个量子点隧道结阵列包括至少两个隧道结，它们彼此平行地耦合，并且彼此相互分离以防止它们之间的单电子隧穿。多个量子点隧道结阵列中的一个包括栅电极，并且施加到栅电极的电压可以改变电子 - 空穴对的数量。上述多个量子点隧道结阵列中的每一个包括分别施加电压的源极和漏极

4. 发明授权

US06770534B2 Ultra small size vertical MOSFET device and method for the manufacture thereof 有权
标题翻译：超小尺寸垂直MOSFET器件及其制造方法
公开(公告)号：US06770534B2
公开(公告)日：2004-08-03
申请号：US10617183
申请日：2003-07-11
申请人： Wonju Cho , Seong Jae Lee , Kyoung Wan Park
发明人： Wonju Cho , Seong Jae Lee , Kyoung Wan Park
IPC分类号： H01L21336
CPC分类号： H01L29/78642 , H01L27/1203 , Y10S977/712 , Y10S977/721 , Y10S977/723 , Y10S977/887
摘要： The present invention relates to an ultra small size vertical MOSFET device having a vertical channel and a source/drain structure and a method for the manufacture thereof by using a silicon on insulator (SOI) substrate. To begin with, a first silicon conductive layer is formed by doping an impurity of a high concentration into a first single crystal silicon layer. Thereafter, a second single crystal silicon layer with the impurity of a low concentration and a second silicon conductive layer with the impurity of the high concentration are formed on the first silicon conductive layer. The second single crystal silicon layer and the second silicon conductive layer are vertically patterned into a predetermined configuration. Subsequently, a gate insulating layer is formed on entire surface. Then, an annealing process is carried out to diffuse the impurities in the first silicon conductive layer and the second silicon conductive layer into the second single crystal layer, thereby forming a source contact, a drain contact and a vertical channel. Finally, a gate electrode is formed on side walls of the vertical channel.
摘要翻译：本发明涉及具有垂直沟道和源极/漏极结构的超小尺寸垂直MOSFET器件及其通过使用绝缘体上硅（SOI）衬底制造的方法。首先，通过将高浓度的杂质掺杂到第一单晶硅层中来形成第一硅导电层。此后，在第一硅导电层上形成具有低浓度杂质的第二单晶硅层和具有高浓度杂质的第二硅导电层。将第二单晶硅层和第二硅导电层垂直图案化成预定构造。随后，在整个表面上形成栅极绝缘层。然后，进行退火处理，以将第一硅导电层和第二硅导电层中的杂质扩散到第二单晶层中，从而形成源极接触，漏极接触和垂直沟道。最后，在垂直通道的侧壁上形成栅电极。

5. 发明授权

US6037198A Method of fabricating SOI wafer 有权
标题翻译：制造SOI晶圆的方法
公开(公告)号：US6037198A
公开(公告)日：2000-03-14
申请号：US139651
申请日：1998-08-25
申请人： Kyoung Wan Park , Seong Jae Lee , Moon Ho Park , Min Cheol Shin , Sang Chul Oh
发明人： Kyoung Wan Park , Seong Jae Lee , Moon Ho Park , Min Cheol Shin , Sang Chul Oh
IPC分类号： H01L21/20 , H01L21/762 , H01C71/00
CPC分类号： H01L21/76262
摘要： The present invention is to fabricate SOI wafer whose the silicon layer is very uniform and the impurity concentration is low. The insulating layer, that is, a composite layer of SiO2 and silicon, is grown on oxide substrate by means of a molecular beam epitaxy fabricating method using silicon as an original material in the oxygen atmosphere. The composite layer of the oxide and silicon is grown according to gradual decreasing the pressure of oxygen atmosphere. A top silicon layer of uniform thickness is grown by means of a molecular beam epitaxy fabricating method using only silicon material consecutively on the composite layer.
摘要翻译：本发明是制造硅层非常均匀且杂质浓度低的SOI晶片。通过在氧气氛中使用硅作为原料的分子束外延制造方法，在氧化物衬底上生长绝缘层，即SiO 2和硅的复合层。氧化物和硅的复合层根据氧气气氛的逐渐降低而生长。通过在复合层上连续使用硅材料的分子束外延制造方法生长均匀厚度的顶部硅层。

6. 发明授权

US5940696A Method of manufacturing a quantum diffraction transistor 失效
$Method of manufacturing a quantum diffraction transistor$
标题翻译：量子衍射晶体管的制造方法
公开(公告)号：US5940696A
公开(公告)日：1999-08-17
申请号：US932616
申请日：1997-09-17
申请人： Kyoung Wan Park , Seong Jae Lee , Min Cheol Shin
发明人： Kyoung Wan Park , Seong Jae Lee , Min Cheol Shin
IPC分类号： H01L29/06 , H01L21/335 , H01L29/66 , H01L29/772 , H01L29/80 , H01L21/338
CPC分类号： B82Y10/00 , H01L29/66446 , H01L29/66977 , H01L29/772 , Y10S438/962
摘要： The present invention discloses a technique for applying diffraction characteristics of electrons to a two-dimensional electronic device to manufacture multi-functional transistor having various ON/OFF states. Method of manufacturing a quantum diffraction transistor according to the present invention is capable of adjusting the amplitude of drain current and having various ON/OFF states utilizing diffraction characteristics of electrons by interposing a reflection-type diffraction grating in a bent electron path. In the inventive multi-functional quantum diffraction transistor using a two dimensional electron gas in quantum well structure formed at a different species junction in a heterostructure semiconductor device and having a bent electron path between the source electrode and the drain electrode with a reflection-type diffraction grating, the quantum diffraction effect of the electrons is used for the control of the diffracted drain current.
摘要翻译：本发明公开了一种将电子衍射特性应用于二维电子器件以制造具有各种ON / OFF状态的多功能晶体管的技术。根据本发明的量子衍射晶体管的制造方法能够通过在弯曲的电子路径中插入反射型衍射光栅来利用电子的衍射特性来调节漏极电流的振幅并具有各种导通/截止状态。在本发明的多功能量子衍射晶体管中，使用在异质结构半导体器件中形成于不同物质结的量子阱结构中的二维电子气，并且在源电极和漏电极之间具有反射型衍射光栅，电子的量子衍射效应用于衍射漏极电流的控制。

7. 发明授权

US06638823B2 Ultra small size vertical MOSFET device and method for the manufacture thereof 失效
标题翻译：超小尺寸垂直MOSFET器件及其制造方法
公开(公告)号：US06638823B2
公开(公告)日：2003-10-28
申请号：US09975963
申请日：2001-10-15
申请人： Wonju Cho , Seong Jae Lee , Kyoung Wan Park
发明人： Wonju Cho , Seong Jae Lee , Kyoung Wan Park
IPC分类号： H01L218242
CPC分类号： H01L29/78642 , H01L27/1203 , Y10S977/712 , Y10S977/721 , Y10S977/723 , Y10S977/887
摘要： The present invention relates to an ultra small size vertical MOSFET device having a vertical channel and a source/drain structure and a method for the manufacture thereof by using a silicon on insulator (SOI) substrate. To begin with, a first silicon conductive layer is formed by doping an impurity of a high concentration into a first single crystal silicon layer. Thereafter, a second single crystal silicon layer with the impurity of a low concentration and a second silicon conductive layer with the impurity of the high concentration are formed on the first silicon conductive layer. The second single crystal silicon layer and the second silicon conductive layer are vertically patterned into a predetermined configuration. Subsequently, a gate insulating layer is formed on entire surface. Then, an annealing process is carried out to diffuse the impurities in the first silicon conductive layer and the second silicon conductive layer into the second single crystal layer, thereby forming a source region, a drain region and a vertical channel. Finally, a gate electrode is formed on side walls of the vertical channel.
摘要翻译：本发明涉及具有垂直沟道和源极/漏极结构的超小尺寸垂直MOSFET器件及其通过使用绝缘体上硅（SOI）衬底制造的方法。首先，通过将高浓度的杂质掺杂到第一单晶硅层中来形成第一硅导电层。此后，在第一硅导电层上形成具有低浓度杂质的第二单晶硅层和具有高浓度杂质的第二硅导电层。将第二单晶硅层和第二硅导电层垂直图案化成预定构造。随后，在整个表面上形成栅极绝缘层。然后，进行退火处理，以将第一硅导电层和第二硅导电层中的杂质扩散到第二单晶层中，从而形成源极区，漏极区和垂直沟道。最后，在垂直通道的侧壁上形成栅电极。

8. 发明授权

US5994714A Quantum diffraction transistor 失效
$Quantum diffraction transistor$
标题翻译：量子衍射晶体管
公开(公告)号：US5994714A
公开(公告)日：1999-11-30
申请号：US932189
申请日：1997-09-17
申请人： Kyoung Wan Park , Seong Jae Lee , Min Cheol Shin
发明人： Kyoung Wan Park , Seong Jae Lee , Min Cheol Shin
IPC分类号： H01L29/06 , H01L21/335 , H01L29/66 , H01L29/772 , H01L29/80 , H01L29/775 , H01L29/778
CPC分类号： B82Y10/00 , H01L29/66446 , H01L29/66977 , H01L29/772 , Y10S438/962
摘要： The present invention discloses a technique for applying diffraction characteristic of electrons to a two-dimensional electronic device to manufacture multi-functional transistor having various ON/OFF states. A quantum diffraction transistor according to the present invention is capable of adjusting the amplitude of drain current and having various ON/OFF states utilizing diffraction characteristic of electrons by interposing a reflection-type diffraction grating in an electron path. The inventive multi-functional quantum diffraction transistor uses a two dimensional electron gas in formed at a different species junction in a semiconductor heterostructure, and has a bent electron path between the source electrode and the drain electrode with a reflection-type diffraction grating. The quantum diffraction effect of the electrons is used for the control of the diffracted drain current.
摘要翻译：本发明公开了一种将电子衍射特性应用于二维电子器件以制造具有各种ON / OFF状态的多功能晶体管的技术。根据本发明的量子衍射晶体管能够通过在电子路径中插入反射型衍射光栅来利用电子的衍射特性来调节漏极电流的振幅并具有各种导通/截止状态。本发明的多功能量子衍射晶体管使用在半导体异质结构中的不同物质结处形成的二维电子气体，并且在反射型衍射光栅之间具有在源电极和漏电极之间的弯曲电子路径。电子的量子衍射效应用于衍射漏极电流的控制。

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