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    • 5. 发明授权
    • Tape substrate and method for fabricating the same
    • 胶带基材及其制造方法
    • US07180006B2
    • 2007-02-20
    • US10724219
    • 2003-12-01
    • Soon Bog KwonSang Hun LeeYang Sik MoonKi Pyo HongYoon Kuen Cho
    • Soon Bog KwonSang Hun LeeYang Sik MoonKi Pyo HongYoon Kuen Cho
    • B32B3/00H05K1/09
    • H05K3/244H01L23/49572H01L23/49582H01L2924/0002H05K1/0393H05K3/28H05K2201/0397H05K2203/1105Y10S428/901Y10T29/49155Y10T29/4916Y10T428/24917Y10T428/325H01L2924/00
    • A tape substrate including an insulating film, a copper foil pattern formed on the insulating film at one side of the insulating film, and provided with a connecting area where an electronic element is to be mounted, a barrier layer plated on the copper foil pattern at the connecting area, and formed with a plurality of pores, and a tin layer plated on the barrier layer, and alloyed with a portion of the copper foil pattern corresponding to the connecting area, through the pores. A method for fabricating the tape substrate is also disclosed. In accordance with the invention, it is possible to reduce the time taken for the copper foil pattern to come into contact with the electroless tin plating solution used in the tin plating process, thereby preventing the copper component of the copper foil pattern from being eluted. Accordingly, there is no open-circuit fault caused by formation of pores. The barrier layer makes it possible to obtain an improved plating efficiency and to reduce the thickness of the alloy layer. In addition, the barrier layer serves to reduce internal stress generated at the interface between the tin layer and the copper foil pattern, thereby suppressing formation of voids. Accordingly, there is an effect of preventing a short circuit caused by the growth of whiskers.
    • 一种带状基板,包括绝缘膜,在绝缘膜的一侧上的绝缘膜上形成的铜箔图案,并且设置有要安装电子元件的连接区域,镀在铜箔图案上的阻挡层 连接区域,并且形成有多个孔,以及镀在阻挡层上的锡层,并且与对应于连接区域的铜箔图案的一部分合金化。 还公开了一种用于制造带基材的方法。 根据本发明,可以减少铜箔图案与镀锡工艺中使用的化学镀锡溶液接触所花费的时间,从而防止铜箔图案的铜成分被洗脱。 因此,没有由孔形成引起的开路故障。 阻挡层可以获得提高的电镀效率并减小合金层的厚度。 此外,阻挡层用于减少在锡层和铜箔图案之间的界面处产生的内应力,从而抑制空隙的形成。 因此,存在防止晶须生长引起的短路的效果。