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1. 发明授权

US08791580B2 Integrated circuit packages having redistribution structures 有权
标题翻译：具有再分配结构的集成电路封装
公开(公告)号：US08791580B2
公开(公告)日：2014-07-29
申请号：US13610077
申请日：2012-09-11
申请人： Chul Park , Sun-Won Kang , Kil-Soo Kim , Joong-Hyun Baek
发明人： Chul Park , Sun-Won Kang , Kil-Soo Kim , Joong-Hyun Baek
IPC分类号： H01L23/48
CPC分类号： H01L23/4951 , H01L23/49531 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/48227 , H01L2224/4824 , H01L2224/48247 , H01L2224/4911 , H01L2224/49175 , H01L2225/06506 , H01L2225/06527 , H01L2225/06562 , H01L2924/00014 , H01L2924/19107 , H01L2224/45099 , H01L2924/00 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor package includes a semiconductor chip stack disposed between first and second leads near first and second sides of the package and including a plurality of semiconductor chips, and a redistribution structure disposed on the semiconductor chip stack. At least one semiconductor chip of the semiconductor chip stack includes a plurality of first chip pads disposed near or closer to a third side of the package. The redistribution structure includes a first redistribution pad disposed near or closer to the first side and electrically connected to the first lead, a second redistribution pad disposed near or closer to the second side and electrically connected to the second lead, and a third redistribution pad disposed near or closer to the third side and electrically connected to a first one of the first chip pads and the first redistribution pad.
摘要翻译：半导体封装包括设置在封装的第一和第二侧附近的第一和第二引线之间的半导体芯片堆叠，并且包括多个半导体芯片以及设置在半导体芯片堆叠上的再分配结构。半导体芯片堆叠的至少一个半导体芯片包括设置在封装的第三侧附近或更接近第三侧的多个第一芯片焊盘。再分配结构包括设置在第一侧附近或更靠近第一侧并且电连接到第一引线的第一再分配焊盘，设置在第二侧附近或更靠近第二侧并与第二引线电连接的第二再分布焊盘，靠近或更靠近第三侧并且电连接到第一芯片焊盘和第一再分布焊盘中的第一芯片焊盘。

2. 发明授权

US08143693B2 Semiconductor device including redistribution line structure and method of fabricating the same 有权
标题翻译：包括再分布线结构的半导体器件及其制造方法
公开(公告)号：US08143693B2
公开(公告)日：2012-03-27
申请号：US12098352
申请日：2008-04-04
申请人： Seung-Duk Baek , Sun-Won Kang , Hyun-Soo Chung
发明人： Seung-Duk Baek , Sun-Won Kang , Hyun-Soo Chung
IPC分类号： H01L29/00
CPC分类号： H01L23/525 , H01L23/16 , H01L23/3114 , H01L23/3192 , H01L23/562 , H01L24/02 , H01L2224/02233 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/014 , H01L2924/05042 , H01L2924/181 , H01L2924/00
摘要： The invention provides a semiconductor device. The semiconductor device includes a semiconductor chip having an active surface on which pads are disposed, a passivation layer pattern disposed to cover the active surface of the semiconductor chip and to expose the pads, a first insulation layer pattern disposed on the passivation layer pattern, a second insulation layer pattern disposed on only a portion of the first insulation layer pattern, and redistribution line patterns electrically connected to the pads and disposed so as to extend across the second insulation layer pattern and the first insulation layer pattern. A method of fabricating the same is also provided.
摘要翻译：本发明提供一种半导体器件。半导体器件包括具有布置有焊盘的有源表面的半导体芯片，布置成覆盖半导体芯片的有源表面并暴露焊盘的钝化层图案，设置在钝化层图案上的第一绝缘层图案，第二绝缘层图案仅设置在第一绝缘层图案的一部分上，再分布线图形电连接到焊盘并且被设置成跨越第二绝缘层图案和第一绝缘层图案延伸。还提供了一种制造该方法的方法。

3. 发明申请

US20100102434A1 SEMICONDUCTOR MEMORY DEVICE HAVING IMPROVED VOLTAGE TRANSMISSION PATH AND DRIVING METHOD THEREOF 有权
标题翻译：具有改进的电压传输路径的半导体存储器件及其驱动方法
公开(公告)号：US20100102434A1
公开(公告)日：2010-04-29
申请号：US12652875
申请日：2010-01-06
申请人： Sun-Won Kang , Seung-Duk Baek
发明人： Sun-Won Kang , Seung-Duk Baek
IPC分类号： H01L25/16 , H01L23/498
CPC分类号： G11C5/063 , H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Provided are a semiconductor memory device and a method of driving the device which can improve a noise characteristic of a voltage signal supplied to a memory cell of the device. The semiconductor memory device includes a first semiconductor chip and one or more second semiconductor chips stacked on the first chip. The first chip includes an input/output circuit for sending/receiving a voltage signal, a data signal, and a control signal to/from an outside system. The one or more second semiconductor chips each include a memory cell region for storing data. The second semiconductor chips receive at least one signal through one or more signal paths that are formed outside the input/output circuit of the first chip.
摘要翻译：提供一种半导体存储器件和驱动器件的方法，该器件可以改善提供给器件的存储单元的电压信号的噪声特性。半导体存储器件包括第一半导体芯片和堆叠在第一芯片上的一个或多个第二半导体芯片。第一芯片包括用于向/从外部系统发送/接收电压信号，数据信号和控制信号的输入/输出电路。一个或多个第二半导体芯片各自包括用于存储数据的存储单元区域。第二半导体芯片通过形成在第一芯片的输入/输出电路外部的一个或多个信号路径接收至少一个信号。

4. 发明申请

US20100090326A1 Stack package 有权
标题翻译：堆栈包
公开(公告)号：US20100090326A1
公开(公告)日：2010-04-15
申请号：US12588382
申请日：2009-10-14
申请人： Seung-Duk Baek , Sun-Won Kang , Jong-Joo Lee
发明人： Seung-Duk Baek , Sun-Won Kang , Jong-Joo Lee
IPC分类号： H01L25/065
CPC分类号： H01L25/0657 , H01L23/13 , H01L23/3128 , H01L23/481 , H01L23/49816 , H01L24/48 , H01L2224/06136 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/73257 , H01L2225/0651 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A stack package may include a substrate having first and second faces opposite each other and an opening formed therein. The first semiconductor chip may be mounted on the first face of the substrate and include a through electrode in the middle region of the first semiconductor chip that is exposed through the opening. The second semiconductor chip may be stacked on the first semiconductor chip and electrically connected to the first semiconductor chip by the through electrode of the first semiconductor chip. The circuit pattern may be formed on the second face of the substrate and include a bonding pad arranged adjacent to the opening and electrically connected to the through electrode of the first semiconductor chip through the opening, an outer connection pad spaced apart from the bonding pad and a connection wiring extending from the opening to the outer connection pad via the bonding pad.
摘要翻译：堆叠包装可以包括具有彼此相对的第一和第二面以及其中形成的开口的衬底。第一半导体芯片可以安装在基板的第一面上，并且在通过开口暴露的第一半导体芯片的中间区域中包括通孔。第二半导体芯片可以堆叠在第一半导体芯片上并且通过第一半导体芯片的通孔电连接到第一半导体芯片。电路图案可以形成在基板的第二面上，并且包括邻近开口布置的焊盘，并且通过开口电连接到第一半导体芯片的通孔，与焊盘间隔开的外连接焊盘和连接配线，从连接焊盘的开口延伸到外部连接焊盘。

5. 发明申请

US20070139062A1 TEST PROBE FOR SEMICONDUCTOR PACKAGE 失效
标题翻译：半导体封装的测试探针
公开(公告)号：US20070139062A1
公开(公告)日：2007-06-21
申请号：US11677017
申请日：2007-02-20
申请人： Sun-Won Kang
发明人： Sun-Won Kang
IPC分类号： G01R31/02
CPC分类号： G01R1/06733 , G01R1/06738
摘要： An embodiment may comprise a test probe to measure electrical properties of a semiconductor package having ball-shaped terminals. The probe may include a signal tip and a ground tip. The signal tip may have a spherical lower surface allowing good contact with a ball-shaped signal terminal. The ground tip may be extended from a lower end of a ground barrel that encloses the signal tip. The ground tip may move independent of the signal tip by means of a barrel stopper and a spring. Thus, the probe can be used regardless of the size of and the distance between the package terminals.
摘要翻译：实施例可以包括用于测量具有球形端子的半导体封装的电特性的测试探针。探头可以包括信号尖端和接地尖端。信号尖端可以具有允许与球形信号端子良好接触的球形下表面。接地尖端可以从包围信号尖端的接地筒的下端延伸。接地尖端可以通过镜筒塞和弹簧独立于信号尖端移动。因此，可以使用探针，而不管封装端子之间的尺寸和距离。

6. 发明申请

US20070001282A1 Three-dimensional semiconductor module having multi-sided ground block 有权
标题翻译：具有多面接地块的三维半导体模块
公开(公告)号：US20070001282A1
公开(公告)日：2007-01-04
申请号：US11369444
申请日：2006-03-06
申请人： Sun-Won Kang , Seung-Duk Baek
发明人： Sun-Won Kang , Seung-Duk Baek
IPC分类号： H01L23/52
CPC分类号： G11C5/04 , B81B7/0074 , H01L23/3677 , H01L23/467 , H01L23/49838 , H01L23/50 , H01L23/5385 , H01L23/5387 , H01L25/065 , H01L2224/16 , H01L2224/16225 , H01L2924/15192 , H01L2924/19107 , H05K1/189 , H05K3/0061 , H05K2201/056
摘要： The present invention relates to a three-dimensional semiconductor module having at least one unit semiconductor device connected to the outer-facing side surfaces of a multi-side ground block. The unit semiconductor device has a structure in which a semiconductor package (or semiconductor chip) is mounted on a unit wiring substrate. Ground pads to be connected to the outer-facing side surfaces of the ground block are formed on the first surface of the unit wiring substrate, the semiconductor chip is mounted on the second surface opposite to the first surface, and contact terminals electrically connected to the semiconductor chip are formed on the second surface.
摘要翻译：本发明涉及一种三维半导体模块，其具有连接到多侧接地块的面向外侧面的至少一个单元半导体器件。单元半导体器件具有半导体封装（或半导体芯片）安装在单元布线基板上的结构。在单元布线基板的第一表面上形成要连接到接地块的面向外侧的接地焊盘，半导体芯片安装在与第一表面相对的第二表面上，并且接触端子电连接到半导体芯片形成在第二表面上。

7. 发明授权

US08153521B2 Wafer-level stack package 有权
标题翻译：晶圆级堆栈包
公开(公告)号：US08153521B2
公开(公告)日：2012-04-10
申请号：US12962934
申请日：2010-12-08
申请人： Sun-Won Kang , Seung-Duk Baek
发明人： Sun-Won Kang , Seung-Duk Baek
IPC分类号： H01L21/50
CPC分类号： H01L25/0657 , H01L21/76898 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05548 , H01L2224/16 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/05099
摘要： A wafer-level stack package includes semiconductor chips, first connection members, a second connection member, a substrate and an external connection terminal. The semiconductor chips have a power/ground pad and a signal pad. The first connection members are electrically connected to the power/ground pad and the signal pad of each of the semiconductor chips. The second connection member is electrically connected to at least one of the power/ground pads of each of the semiconductor chips, the power/ground pads being connected to the first connection members. The substrate supports the stacked semiconductor chips, the substrate including wirings that are electrically connected to the first connection members and the second connection member. The external connection terminal is provided on a surface of the substrate opposite to a surface where the semiconductor chips are stacked, wherein the external connection terminals are electrically connected to the wirings, respectively.
摘要翻译：晶圆级堆叠封装包括半导体芯片，第一连接构件，第二连接构件，基板和外部连接端子。半导体芯片具有电源/接地焊盘和信号焊盘。第一连接构件电连接到电源/接地焊盘和每个半导体芯片的信号焊盘。第二连接构件电连接到每个半导体芯片的功率/接地焊盘中的至少一个，电源/接地焊盘连接到第一连接构件。基板支撑层叠的半导体芯片，基板包括电连接到第一连接构件和第二连接构件的布线。外部连接端子设置在与半导体芯片堆叠的表面相对的表面上，其中外部连接端子分别电连接到布线。

8. 发明授权

US08115324B2 Semiconductor module 有权
标题翻译：半导体模块
公开(公告)号：US08115324B2
公开(公告)日：2012-02-14
申请号：US12292196
申请日：2008-11-13
申请人： Sun-Won Kang , Young-Hee Song , Tae-Gyeong Chung , Nam-Seog Kim , Seung-Duk Baek
发明人： Sun-Won Kang , Young-Hee Song , Tae-Gyeong Chung , Nam-Seog Kim , Seung-Duk Baek
IPC分类号： H01L29/40
CPC分类号： H01L25/0657 , H01L24/06 , H01L2224/0401 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/49113 , H01L2224/85399 , H01L2225/0651 , H01L2225/06527 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die.
摘要翻译：半导体模块可以包括在电路基板上具有第一裸片的电路基板和在第一裸片上的第二裸片。第一裸片可以包括在第一裸片的第一周边部分上的至少一个第一数据输入/输出焊盘和第三外围部分上的至少一个第一控制/地址焊盘，第三外围部分与第一外围部分的第一外围部分分离第一个死亡第二管芯可以包括在第二外围部分上的至少一个第二数据输入/输出焊盘和第四外围部分上的至少一个第二控制/地址焊盘。第二模具的第二周边部分在平面图中不与第一模具的第一周边部分重叠。第二模具的第四周边部分与第一模具的第三周边部分的至少一部分重叠。

9. 发明授权

US08039928B2 Chip stack package 有权
标题翻译：芯片堆栈封装
公开(公告)号：US08039928B2
公开(公告)日：2011-10-18
申请号：US12171035
申请日：2008-07-10
申请人： Sun-Won Kang , Seung-Duk Baek , Jong-Joo Lee
发明人： Sun-Won Kang , Seung-Duk Baek , Jong-Joo Lee
IPC分类号： H01L23/538
CPC分类号： H01L25/0657 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2924/15311
摘要： A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities.
摘要翻译：芯片堆叠包括通过使用粘合剂层作为中间介质堆叠的多个芯片，以及通过芯片形成的通孔电极以电耦合芯片。通孔电极通过通孔电极，通过通孔电极的接地或通过通孔电极的信号传输分类为电源。通过通孔电极和通过通孔电极的接地的电源由诸如铜的第一材料形成，并且通过通孔电极的信号传输由掺杂杂质的多晶硅等第二材料形成。通过通孔电极的信号传输可以具有比通过通孔电极和通过通孔电极的接地的每个电源的直径更小的横截面，而不管其电阻率如何。

10. 发明申请

US20110157952A1 SEMICONDUCTOR MEMORY DEVICE HAVING IMPROVED VOLTAGE TRANSMISSION PATH AND DRIVING METHOD THEREOF 有权
标题翻译：具有改进的电压传输路径的半导体存储器件及其驱动方法
公开(公告)号：US20110157952A1
公开(公告)日：2011-06-30
申请号：US13042049
申请日：2011-03-07
申请人： Sun-Won Kang , Seung-Duk Baek
发明人： Sun-Won Kang , Seung-Duk Baek
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Provided are a semiconductor memory device and a method of driving the device which can improve a noise characteristic of a voltage signal supplied to a memory cell of the device. The semiconductor memory device includes a first semiconductor chip and one or more second semiconductor chips stacked on the first chip. The first chip includes an input/output circuit for sending/receiving a voltage signal, a data signal, and a control signal to/from an outside system. The one or more second semiconductor chips each include a memory cell region for storing data. The second semiconductor chips receive at least one signal through one or more signal paths that are formed outside the input/output circuit of the first chip.
摘要翻译：提供一种半导体存储器件和驱动器件的方法，该器件可以改善提供给器件的存储单元的电压信号的噪声特性。半导体存储器件包括第一半导体芯片和堆叠在第一芯片上的一个或多个第二半导体芯片。第一芯片包括用于向/从外部系统发送/接收电压信号，数据信号和控制信号的输入/输出电路。一个或多个第二半导体芯片各自包括用于存储数据的存储单元区域。第二半导体芯片通过形成在第一芯片的输入/输出电路外部的一个或多个信号路径接收至少一个信号。

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