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1. 发明授权

US08791580B2 Integrated circuit packages having redistribution structures 有权
标题翻译：具有再分配结构的集成电路封装
公开(公告)号：US08791580B2
公开(公告)日：2014-07-29
申请号：US13610077
申请日：2012-09-11
申请人： Chul Park , Sun-Won Kang , Kil-Soo Kim , Joong-Hyun Baek
发明人： Chul Park , Sun-Won Kang , Kil-Soo Kim , Joong-Hyun Baek
IPC分类号： H01L23/48
CPC分类号： H01L23/4951 , H01L23/49531 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/48227 , H01L2224/4824 , H01L2224/48247 , H01L2224/4911 , H01L2224/49175 , H01L2225/06506 , H01L2225/06527 , H01L2225/06562 , H01L2924/00014 , H01L2924/19107 , H01L2224/45099 , H01L2924/00 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor package includes a semiconductor chip stack disposed between first and second leads near first and second sides of the package and including a plurality of semiconductor chips, and a redistribution structure disposed on the semiconductor chip stack. At least one semiconductor chip of the semiconductor chip stack includes a plurality of first chip pads disposed near or closer to a third side of the package. The redistribution structure includes a first redistribution pad disposed near or closer to the first side and electrically connected to the first lead, a second redistribution pad disposed near or closer to the second side and electrically connected to the second lead, and a third redistribution pad disposed near or closer to the third side and electrically connected to a first one of the first chip pads and the first redistribution pad.
摘要翻译：半导体封装包括设置在封装的第一和第二侧附近的第一和第二引线之间的半导体芯片堆叠，并且包括多个半导体芯片以及设置在半导体芯片堆叠上的再分配结构。半导体芯片堆叠的至少一个半导体芯片包括设置在封装的第三侧附近或更接近第三侧的多个第一芯片焊盘。再分配结构包括设置在第一侧附近或更靠近第一侧并且电连接到第一引线的第一再分配焊盘，设置在第二侧附近或更靠近第二侧并与第二引线电连接的第二再分布焊盘，靠近或更靠近第三侧并且电连接到第一芯片焊盘和第一再分布焊盘中的第一芯片焊盘。

2. 发明授权

US08143693B2 Semiconductor device including redistribution line structure and method of fabricating the same 有权
标题翻译：包括再分布线结构的半导体器件及其制造方法
公开(公告)号：US08143693B2
公开(公告)日：2012-03-27
申请号：US12098352
申请日：2008-04-04
申请人： Seung-Duk Baek , Sun-Won Kang , Hyun-Soo Chung
发明人： Seung-Duk Baek , Sun-Won Kang , Hyun-Soo Chung
IPC分类号： H01L29/00
CPC分类号： H01L23/525 , H01L23/16 , H01L23/3114 , H01L23/3192 , H01L23/562 , H01L24/02 , H01L2224/02233 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/014 , H01L2924/05042 , H01L2924/181 , H01L2924/00
摘要： The invention provides a semiconductor device. The semiconductor device includes a semiconductor chip having an active surface on which pads are disposed, a passivation layer pattern disposed to cover the active surface of the semiconductor chip and to expose the pads, a first insulation layer pattern disposed on the passivation layer pattern, a second insulation layer pattern disposed on only a portion of the first insulation layer pattern, and redistribution line patterns electrically connected to the pads and disposed so as to extend across the second insulation layer pattern and the first insulation layer pattern. A method of fabricating the same is also provided.
摘要翻译：本发明提供一种半导体器件。半导体器件包括具有布置有焊盘的有源表面的半导体芯片，布置成覆盖半导体芯片的有源表面并暴露焊盘的钝化层图案，设置在钝化层图案上的第一绝缘层图案，第二绝缘层图案仅设置在第一绝缘层图案的一部分上，再分布线图形电连接到焊盘并且被设置成跨越第二绝缘层图案和第一绝缘层图案延伸。还提供了一种制造该方法的方法。

3. 发明授权

US07964948B2 Chip stack, chip stack package, and method of forming chip stack and chip stack package 有权
标题翻译：芯片堆栈，芯片堆栈封装，以及形成芯片堆栈和芯片堆栈封装的方法
公开(公告)号：US07964948B2
公开(公告)日：2011-06-21
申请号：US11790359
申请日：2007-04-25
申请人： Jong-joo Lee , Sun-won Kang
发明人： Jong-joo Lee , Sun-won Kang
IPC分类号： H01L23/02
CPC分类号： H01L23/3128 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73257 , H01L2224/73265 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/181 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A chip stack may include a first chip and a second chip stacked on the first chip. Each of the first and second chips may include a substrate having an active surface and an inactive surface opposite to the active surface; an internal circuit in the active surface; an I/O chip pad on the active surface and connected to the internal circuit through an I/O buffer; and a I/O connection pad connected to the I/O chip pad through the I/O buffer by a circuit wiring. A redistributed I/O chip pad layer may be on the active surface of the first chip, the redistributed I/O chip pad layer redistributing the I/O chip pad. The I/O connection pads of the first chip and the second chip may be electrically connected to each other by an electrical connecting part.
摘要翻译：芯片堆叠可以包括堆叠在第一芯片上的第一芯片和第二芯片。第一和第二芯片中的每一个可以包括具有活性表面和与活性表面相对的非活性表面的基底; 活动表面内部电路; 有源表面上的I / O芯片焊盘，并通过I / O缓冲器连接到内部电路; 以及通过I / O缓冲器通过电路布线连接到I / O芯片焊盘的I / O连接焊盘。再分布的I / O芯片焊盘层可以在第一芯片的有源表面上，重新分布的I / O芯片焊盘层重新分布I / O芯片焊盘。第一芯片和第二芯片的I / O连接焊盘可以通过电连接部分彼此电连接。

4. 发明授权

US07851256B2 Method of manufacturing chip-on-chip semiconductor device 有权
标题翻译：片上芯片半导体器件的制造方法
公开(公告)号：US07851256B2
公开(公告)日：2010-12-14
申请号：US12285923
申请日：2008-10-16
申请人： Hyun-soo Chung , Dong-ho Lee , Seong-deok Hwang , Sun-won Kang , Seung-duk Baek
发明人： Hyun-soo Chung , Dong-ho Lee , Seong-deok Hwang , Sun-won Kang , Seung-duk Baek
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L25/0657 , H01L24/02 , H01L24/16 , H01L25/50 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/13023 , H01L2224/13024 , H01L2224/16112 , H01L2224/16147 , H01L2224/16237 , H01L2224/2518 , H01L2224/81141 , H01L2224/81191 , H01L2224/81365 , H01L2224/81385 , H01L2224/81805 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/014
摘要： Provided is a method of fabricating a chip-on-chip (COC) semiconductor device. The method of fabricating a chip-on-chip (COC) semiconductor device may include preparing a first semiconductor device with a metal wiring having at least one discontinuous spot formed therein, preparing a second semiconductor device with at least one bump formed on a surface of the second semiconductor device corresponding to the at least one discontinuous spot, aligning the first semiconductor device onto the second semiconductor device, and connecting the at least one bump of the second semiconductor device to the at least one discontinuous spot formed in the metal wiring of the first semiconductor device.
摘要翻译：提供了一种制造片上芯片（COC）半导体器件的方法。片上芯片（COC）半导体器件的制造方法可以包括：准备具有在其中形成有至少一个不连续点的金属布线的第一半导体器件，制备第二半导体器件，其中至少一个凸点形成在所述第二半导体器件对应于所述至少一个不连续点，将所述第一半导体器件对准到所述第二半导体器件上，并且将所述第二半导体器件的所述至少一个突起连接到形成在所述第二半导体器件的所述金属布线中的所述至少一个不连续点第一半导体器件。

5. 发明申请

US20100102434A1 SEMICONDUCTOR MEMORY DEVICE HAVING IMPROVED VOLTAGE TRANSMISSION PATH AND DRIVING METHOD THEREOF 有权
标题翻译：具有改进的电压传输路径的半导体存储器件及其驱动方法
公开(公告)号：US20100102434A1
公开(公告)日：2010-04-29
申请号：US12652875
申请日：2010-01-06
申请人： Sun-Won Kang , Seung-Duk Baek
发明人： Sun-Won Kang , Seung-Duk Baek
IPC分类号： H01L25/16 , H01L23/498
CPC分类号： G11C5/063 , H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Provided are a semiconductor memory device and a method of driving the device which can improve a noise characteristic of a voltage signal supplied to a memory cell of the device. The semiconductor memory device includes a first semiconductor chip and one or more second semiconductor chips stacked on the first chip. The first chip includes an input/output circuit for sending/receiving a voltage signal, a data signal, and a control signal to/from an outside system. The one or more second semiconductor chips each include a memory cell region for storing data. The second semiconductor chips receive at least one signal through one or more signal paths that are formed outside the input/output circuit of the first chip.
摘要翻译：提供一种半导体存储器件和驱动器件的方法，该器件可以改善提供给器件的存储单元的电压信号的噪声特性。半导体存储器件包括第一半导体芯片和堆叠在第一芯片上的一个或多个第二半导体芯片。第一芯片包括用于向/从外部系统发送/接收电压信号，数据信号和控制信号的输入/输出电路。一个或多个第二半导体芯片各自包括用于存储数据的存储单元区域。第二半导体芯片通过形成在第一芯片的输入/输出电路外部的一个或多个信号路径接收至少一个信号。

6. 发明申请

US20100090326A1 Stack package 有权
标题翻译：堆栈包
公开(公告)号：US20100090326A1
公开(公告)日：2010-04-15
申请号：US12588382
申请日：2009-10-14
申请人： Seung-Duk Baek , Sun-Won Kang , Jong-Joo Lee
发明人： Seung-Duk Baek , Sun-Won Kang , Jong-Joo Lee
IPC分类号： H01L25/065
CPC分类号： H01L25/0657 , H01L23/13 , H01L23/3128 , H01L23/481 , H01L23/49816 , H01L24/48 , H01L2224/06136 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/73257 , H01L2225/0651 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A stack package may include a substrate having first and second faces opposite each other and an opening formed therein. The first semiconductor chip may be mounted on the first face of the substrate and include a through electrode in the middle region of the first semiconductor chip that is exposed through the opening. The second semiconductor chip may be stacked on the first semiconductor chip and electrically connected to the first semiconductor chip by the through electrode of the first semiconductor chip. The circuit pattern may be formed on the second face of the substrate and include a bonding pad arranged adjacent to the opening and electrically connected to the through electrode of the first semiconductor chip through the opening, an outer connection pad spaced apart from the bonding pad and a connection wiring extending from the opening to the outer connection pad via the bonding pad.
摘要翻译：堆叠包装可以包括具有彼此相对的第一和第二面以及其中形成的开口的衬底。第一半导体芯片可以安装在基板的第一面上，并且在通过开口暴露的第一半导体芯片的中间区域中包括通孔。第二半导体芯片可以堆叠在第一半导体芯片上并且通过第一半导体芯片的通孔电连接到第一半导体芯片。电路图案可以形成在基板的第二面上，并且包括邻近开口布置的焊盘，并且通过开口电连接到第一半导体芯片的通孔，与焊盘间隔开的外连接焊盘和连接配线，从连接焊盘的开口延伸到外部连接焊盘。

7. 发明申请

US20070252271A1 SEMICONDUCTOR MEMORY MODULE HAVING AN OBLIQUE MEMORY CHIP 失效
标题翻译：具有OBLIQUE MEMORY CHIP的半导体存储器模块
公开(公告)号：US20070252271A1
公开(公告)日：2007-11-01
申请号：US11740821
申请日：2007-04-26
申请人： Joong-Hyun BAEK , Sun-Won KANG , Moon-Jung KIM , Hyung-Gil BAEK , Hee-Jin LEE
发明人： Joong-Hyun BAEK , Sun-Won KANG , Moon-Jung KIM , Hyung-Gil BAEK , Hee-Jin LEE
IPC分类号： H01L23/34
CPC分类号： H01L25/16 , G11C5/04 , H01L21/563 , H01L25/0655 , H01L2224/73203 , H05K1/181 , H05K2201/09409 , H05K2201/09418 , H05K2201/10159 , Y02P70/611
摘要： Provided is a semiconductor memory module allowing a filling member formed between a module substrate and memory chips mounted on the module substrate to completely fill the space between the module substrate and the memory chips. According to embodiments of the present invention, the semiconductor memory module includes a module substrate having at least one memory chip mounted on the substrate such that its edges are oblique to major and minor axes bisecting the module substrate. The oblique orientation allows for an improved opening between memory chips formed on the substrate so that the filling member may be properly formed between the module substrate and the memory chips to prevent voids where the filling member is not formed.
摘要翻译：提供了一种半导体存储器模块，其允许形成在模块基板和安装在模块基板上的存储芯片之间的填充构件完全填充模块基板和存储器芯片之间的空间。根据本发明的实施例，半导体存储器模块包括具有安装在基板上的至少一个存储芯片的模块基板，使得其边缘对于将模块基板平分的主轴和短轴倾斜。倾斜方向允许在基板上形成的存储芯片之间的开口改善，使得填充构件可以适当地形成在模块基板和存储芯片之间，以防止填充构件未形成的空隙。

8. 发明申请

US20070139062A1 TEST PROBE FOR SEMICONDUCTOR PACKAGE 失效
标题翻译：半导体封装的测试探针
公开(公告)号：US20070139062A1
公开(公告)日：2007-06-21
申请号：US11677017
申请日：2007-02-20
申请人： Sun-Won Kang
发明人： Sun-Won Kang
IPC分类号： G01R31/02
CPC分类号： G01R1/06733 , G01R1/06738
摘要： An embodiment may comprise a test probe to measure electrical properties of a semiconductor package having ball-shaped terminals. The probe may include a signal tip and a ground tip. The signal tip may have a spherical lower surface allowing good contact with a ball-shaped signal terminal. The ground tip may be extended from a lower end of a ground barrel that encloses the signal tip. The ground tip may move independent of the signal tip by means of a barrel stopper and a spring. Thus, the probe can be used regardless of the size of and the distance between the package terminals.
摘要翻译：实施例可以包括用于测量具有球形端子的半导体封装的电特性的测试探针。探头可以包括信号尖端和接地尖端。信号尖端可以具有允许与球形信号端子良好接触的球形下表面。接地尖端可以从包围信号尖端的接地筒的下端延伸。接地尖端可以通过镜筒塞和弹簧独立于信号尖端移动。因此，可以使用探针，而不管封装端子之间的尺寸和距离。

9. 发明申请

US20070001282A1 Three-dimensional semiconductor module having multi-sided ground block 有权
标题翻译：具有多面接地块的三维半导体模块
公开(公告)号：US20070001282A1
公开(公告)日：2007-01-04
申请号：US11369444
申请日：2006-03-06
申请人： Sun-Won Kang , Seung-Duk Baek
发明人： Sun-Won Kang , Seung-Duk Baek
IPC分类号： H01L23/52
CPC分类号： G11C5/04 , B81B7/0074 , H01L23/3677 , H01L23/467 , H01L23/49838 , H01L23/50 , H01L23/5385 , H01L23/5387 , H01L25/065 , H01L2224/16 , H01L2224/16225 , H01L2924/15192 , H01L2924/19107 , H05K1/189 , H05K3/0061 , H05K2201/056
摘要： The present invention relates to a three-dimensional semiconductor module having at least one unit semiconductor device connected to the outer-facing side surfaces of a multi-side ground block. The unit semiconductor device has a structure in which a semiconductor package (or semiconductor chip) is mounted on a unit wiring substrate. Ground pads to be connected to the outer-facing side surfaces of the ground block are formed on the first surface of the unit wiring substrate, the semiconductor chip is mounted on the second surface opposite to the first surface, and contact terminals electrically connected to the semiconductor chip are formed on the second surface.
摘要翻译：本发明涉及一种三维半导体模块，其具有连接到多侧接地块的面向外侧面的至少一个单元半导体器件。单元半导体器件具有半导体封装（或半导体芯片）安装在单元布线基板上的结构。在单元布线基板的第一表面上形成要连接到接地块的面向外侧的接地焊盘，半导体芯片安装在与第一表面相对的第二表面上，并且接触端子电连接到半导体芯片形成在第二表面上。

10. 发明申请

US20140339704A1 SEMICONDUCTOR PACKAGE 有权
标题翻译：半导体封装
公开(公告)号：US20140339704A1
公开(公告)日：2014-11-20
申请号：US14279312
申请日：2014-05-15
申请人： Jin-chan Ahn , Sun-won Kang
发明人： Jin-chan Ahn , Sun-won Kang
IPC分类号： H01L23/00
CPC分类号： H01L24/02 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/02375 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05554 , H01L2224/131 , H01L2224/16145 , H01L2224/2919 , H01L2224/32145 , H01L2224/48105 , H01L2224/48111 , H01L2224/48227 , H01L2224/73207 , H01L2224/73253 , H01L2224/73265 , H01L2224/83101 , H01L2225/0651 , H01L2225/06513 , H01L2225/06527 , H01L2225/06558 , H01L2225/06565 , H01L2924/00014 , H01L2924/10161 , H01L2924/181 , H01L2924/014 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package includes a substrate; and first and second semiconductor chips sequentially disposed on the substrate so that active surfaces of the first and second semiconductor chips face each other, wherein the first and second semiconductor chips are center pad-type semiconductor chips each having I/O pads arranged in two columns to be adjacent to a central line thereof, and I/O pads of the second semiconductor chip are electrically connected directly to the substrate without intersecting the central line of the second semiconductor chip.
摘要翻译：半导体封装包括基板; 以及顺序地设置在基板上的第一和第二半导体芯片，使得第一和第二半导体芯片的有效表面彼此面对，其中第一和第二半导体芯片是中心焊盘型半导体芯片，每个具有排列成两列的I / O焊盘与第二半导体芯片的中心线相邻，并且第二半导体芯片的I / O焊盘直接电连接到基板，而不与第二半导体芯片的中心线相交。

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