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1. 发明授权

US07112507B2 MIM capacitor structure and method of fabrication 有权
标题翻译： MIM电容器结构及其制造方法
公开(公告)号：US07112507B2
公开(公告)日：2006-09-26
申请号：US10720450
申请日：2003-11-24
申请人： Sun-Oo Kim , Ernst Demm
发明人： Sun-Oo Kim , Ernst Demm
IPC分类号： H01L21/20
CPC分类号： H01L28/60 , H01L23/5223 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal-insulator-metal (MIM) capacitor wherein a plate of a MIM capacitor is formed in the entire thickness of a metallization layer of a semiconductor device. At least one thin conductive material layer is disposed within the material of the metallization layer to reduce the surface roughness of the metallization layer, thus improving the reliability of the MIM capacitor. The thin conductive material layer may comprise TiN, TaN, or WN and may alternatively comprise a barrier layer disposed over or under the TiN, TaN, or WN. One plate of the MIM capacitor is patterned using the same mask that is used to pattern conductive lines in a metallization layer, thus reducing the number of masks that are required to manufacture the MIM capacitor.
摘要翻译：一种形成金属绝缘体金属（MIM）电容器的方法，其中在半导体器件的金属化层的整个厚度上形成MIM电容器的板。至少一个薄导电材料层设置在金属化层的材料内，以减小金属化层的表面粗糙度，从而提高MIM电容器的可靠性。薄导电材料层可以包括TiN，TaN或WN，并且还可以包括设置在TiN，TaN或WN之上或之下的阻挡层。使用与用于在金属化层中形成导线的掩模相同的掩模对MIM电容器的一个板进行构图，从而减少制造MIM电容器所需的掩模的数量。

2. 发明申请

US20050112836A1 MIM capacitor structure and method of fabrication 有权
标题翻译： MIM电容器结构及其制造方法
公开(公告)号：US20050112836A1
公开(公告)日：2005-05-26
申请号：US10720450
申请日：2003-11-24
申请人： Sun-Oo Kim , Ernst Demm
发明人： Sun-Oo Kim , Ernst Demm
IPC分类号： H01L21/02 , H01L23/522 , H01L21/20 , H01L21/336 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L28/60 , H01L23/5223 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal-insulator-metal (MIM) capacitor wherein a plate of a MIM capacitor is formed in the entire thickness of a metallization layer of a semiconductor device. At least one thin conductive material layer is disposed within the material of the metallization layer to reduce the surface roughness of the metallization layer, thus improving the reliability of the MIM capacitor. The thin conductive material layer may comprise TiN, TaN, or WN and may alternatively comprise a barrier layer disposed over or under the TiN, TaN, or WN. One plate of the MIM capacitor is patterned using the same mask that is used to pattern conductive lines in a metallization layer, thus reducing the number of masks that are required to manufacture the MIM capacitor.
摘要翻译：一种形成金属绝缘体金属（MIM）电容器的方法，其中在半导体器件的金属化层的整个厚度上形成MIM电容器的板。至少一个薄导电材料层设置在金属化层的材料内，以减小金属化层的表面粗糙度，从而提高MIM电容器的可靠性。薄导电材料层可以包括TiN，TaN或WN，并且还可以包括设置在TiN，TaN或WN之上或之下的阻挡层。使用与用于在金属化层中形成导线的掩模相同的掩模对MIM电容器的一个板进行构图，从而减少制造MIM电容器所需的掩模的数量。

3. 发明授权

US07235454B2 MIM capacitor structure and method of fabrication 有权
标题翻译： MIM电容器结构及其制造方法
公开(公告)号：US07235454B2
公开(公告)日：2007-06-26
申请号：US11452159
申请日：2006-06-13
申请人： Sun-Oo Kim , Ernst Demm
发明人： Sun-Oo Kim , Ernst Demm
IPC分类号： H01L21/20
CPC分类号： H01L28/60 , H01L23/5223 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal-insulator-metal (MIM) capacitor wherein a plate of a MIM capacitor is formed in the entire thickness of a metallization layer of a semiconductor device. At least one thin conductive material layer is disposed within the material of the metallization layer to reduce the surface roughness of the metallization layer, thus improving the reliability of the MIM capacitor. The thin conductive material layer may comprise TiN, TaN, or WN and may alternatively comprise a barrier layer disposed over or under the TiN, TaN, or WN. One plate of the MIM capacitor is patterned using the same mask that is used to pattern conductive lines in a metallization layer, thus reducing the number of masks that are required to manufacture the MIM capacitor.
摘要翻译：一种形成金属绝缘体金属（MIM）电容器的方法，其中在半导体器件的金属化层的整个厚度上形成MIM电容器的板。至少一个薄导电材料层设置在金属化层的材料内，以减小金属化层的表面粗糙度，从而提高MIM电容器的可靠性。薄导电材料层可以包括TiN，TaN或WN，并且还可以包括设置在TiN，TaN或WN之上或之下的阻挡层。使用与用于在金属化层中形成导线的掩模相同的掩模对MIM电容器的一个板进行构图，从而减少制造MIM电容器所需的掩模的数量。

4. 发明申请

US20060231920A1 MIM capacitor structure and method of fabrication 有权
公开(公告)号：US20060231920A1
公开(公告)日：2006-10-19
申请号：US11452159
申请日：2006-06-13
申请人： Sun-Oo Kim , Ernst Demm
发明人： Sun-Oo Kim , Ernst Demm
IPC分类号： H01L29/00
CPC分类号： H01L28/60 , H01L23/5223 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal-insulator-metal (MIM) capacitor wherein a plate of a MIM capacitor is formed in the entire thickness of a metallization layer of a semiconductor device. At least one thin conductive material layer is disposed within the material of the metallization layer to reduce the surface roughness of the metallization layer, thus improving the reliability of the MIM capacitor. The thin conductive material layer may comprise TiN, TaN, or WN and may alternatively comprise a barrier layer disposed over or under the TiN, TaN, or WN. One plate of the MIM capacitor is patterned using the same mask that is used to pattern conductive lines in a metallization layer, thus reducing the number of masks that are required to manufacture the MIM capacitor.

5. 发明申请

US20100203701A1 Crack Stop and Moisture Barrier 有权
标题翻译：破裂停止和防潮
公开(公告)号：US20100203701A1
公开(公告)日：2010-08-12
申请号：US12766709
申请日：2010-04-23
申请人： Sun-Oo Kim , O Seo Park
发明人： Sun-Oo Kim , O Seo Park
IPC分类号： H01L21/78 , H01L21/76
CPC分类号： H01L23/585 , H01L23/562 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： A design for a crack stop and moisture barrier for a semiconductor device includes a plurality of discrete conductive features formed at the edge of an integrated circuit proximate a scribe line. The discrete conductive features may comprise a plurality of staggered lines, a plurality of horseshoe-shaped lines, or a combination of both.
摘要翻译：用于半导体器件的裂纹阻挡和湿气屏障的设计包括形成在靠近划线的集成电路的边缘处的多个离散的导电特征。离散的导电特征可以包括多个交错线，多个马蹄形线，或两者的组合。

6. 发明申请

US20100087042A1 Methods of Fabricating Three-Dimensional Capacitor Structures Having Planar Metal-Insulator-Metal and Vertical Capacitors Therein 有权
标题翻译：制造具有平面金属 - 绝缘体 - 金属和垂直电容器的三维电容结构的方法
公开(公告)号：US20100087042A1
公开(公告)日：2010-04-08
申请号：US12246093
申请日：2008-10-06
申请人： Yoon-Hae Kim , Sun-Oo Kim
发明人： Yoon-Hae Kim , Sun-Oo Kim
IPC分类号： H01L21/02
CPC分类号： H01L21/02 , H01L23/5223 , H01L27/0688 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a three-dimensional capacitor network may include forming a first horizontal MIM capacitor on a semiconductor substrate and forming a first interlayer insulating layer on the first horizontal MIM capacitor. A first vertical capacitor electrode is then formed in the first interlayer insulating layer and a second horizontal MIM capacitor is formed on the first interlayer insulating layer. This second horizontal MIM capacitor may be formed by forming an upper capacitor electrode and a lower capacitor electrode. The upper capacitor electrode may be electrically connected by the first vertical capacitor electrode to an upper capacitor electrode of the underlying first MIM capacitor. The lower capacitor electrode, which may be formed in the first interlayer insulating layer, may extend opposite the upper electrodes of the first and second MIM capacitors.
摘要翻译：形成三维电容器网络的方法可以包括在半导体衬底上形成第一水平MIM电容器，并在第一水平MIM电容器上形成第一层间绝缘层。然后在第一层间绝缘层中形成第一垂直电容器电极，并且在第一层间绝缘层上形成第二水平MIM电容器。该第二水平MIM电容器可以通过形成上电容器电极和下电容器电极而形成。上部电容器电极可以通过第一垂直电容器电极电连接到下面的第一MIM电容器的上部电容器电极。可以形成在第一层间绝缘层中的下电容器电极可以与第一和第二MIM电容器的上电极相对延伸。

7. 发明申请

US20050048765A1 Sealed pores in low-k material damascene conductive structures 有权
标题翻译：低k材料镶嵌导电结构中的密封孔
公开(公告)号：US20050048765A1
公开(公告)日：2005-03-03
申请号：US10654143
申请日：2003-09-03
申请人： Sun-Oo Kim
发明人： Sun-Oo Kim
IPC分类号： H01L21/768 , H01L21/331 , H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76807
摘要： An oxide layer is used to seal pores in porous low-dielectric constant materials, thus preventing the migration of subsequently deposited copper materials into the porous low-dielectric constant materials in damascene processes. The oxide layer is deposited over the inner surface of at least one pore along a sidewall of the patterned low-dielectric constant material. In one embodiment, the oxide layer is deposited using atomic layer deposition (ALD), and the oxide layer comprises SiO2.
摘要翻译：使用氧化物层来密封多孔低介电常数材料中的孔，从而防止随后沉积的铜材料在镶嵌工艺中迁移到多孔低介电常数材料中。氧化物层沿图案化的低介电常数材料的侧壁沉积在至少一个孔的内表面上。在一个实施例中，使用原子层沉积（ALD）沉积氧化物层，并且氧化物层包含SiO 2。

8. 发明授权

US08298730B2 Semiconductor devices and methods of manufacturing thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08298730B2
公开(公告)日：2012-10-30
申请号：US13072227
申请日：2011-03-25
申请人： O Seo Park , Sun-Oo Kim , Klaus Herold
发明人： O Seo Park , Sun-Oo Kim , Klaus Herold
IPC分类号： G03F1/20
CPC分类号： H01L23/5226 , G03F1/00 , G03F1/36 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices, methods of manufacturing thereof, lithography masks, and methods of designing lithography masks are disclosed. In one embodiment, a semiconductor device includes a plurality of first features disposed in a first material layer. At least one second feature is disposed in a second material layer, the at least one second feature being disposed over and coupled to the plurality of first features. The at least one second feature includes at least one void disposed between at least two of the plurality of first features.
摘要翻译：公开了半导体器件，其制造方法，光刻掩模和设计光刻掩模的方法。在一个实施例中，半导体器件包括设置在第一材料层中的多个第一特征。至少一个第二特征被布置在第二材料层中，所述至少一个第二特征被布置在多个第一特征上并耦合到多个第一特征。至少一个第二特征包括设置在多个第一特征中的至少两个之间的至少一个空隙。

9. 发明申请

US20110171821A1 Semiconductor Devices and Methods of Manufacturing Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110171821A1
公开(公告)日：2011-07-14
申请号：US13072227
申请日：2011-03-25
申请人： O Seo Park , Sun-Oo Kim , Klaus Herold
发明人： O Seo Park , Sun-Oo Kim , Klaus Herold
IPC分类号： H01L21/4763 , G06F17/50 , G03F1/00
CPC分类号： H01L23/5226 , G03F1/00 , G03F1/36 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices, methods of manufacturing thereof, lithography masks, and methods of designing lithography masks are disclosed. In one embodiment, a semiconductor device includes a plurality of first features disposed in a first material layer. At least one second feature is disposed in a second material layer, the at least one second feature being disposed over and coupled to the plurality of first features. The at least one second feature includes at least one void disposed between at least two of the plurality of first features.
摘要翻译：公开了半导体器件，其制造方法，光刻掩模和设计光刻掩模的方法。在一个实施例中，半导体器件包括设置在第一材料层中的多个第一特征。至少一个第二特征被布置在第二材料层中，所述至少一个第二特征被布置在多个第一特征上并耦合到多个第一特征。至少一个第二特征包括设置在多个第一特征中的至少两个之间的至少一个空隙。

10. 发明授权

US07879681B2 Methods of fabricating three-dimensional capacitor structures having planar metal-insulator-metal and vertical capacitors therein 有权
标题翻译：制造其中具有平面金属 - 绝缘体金属和垂直电容器的三维电容器结构的方法
公开(公告)号：US07879681B2
公开(公告)日：2011-02-01
申请号：US12246093
申请日：2008-10-06
申请人： Yoon-Hae Kim , Sun-Oo Kim
发明人： Yoon-Hae Kim , Sun-Oo Kim
IPC分类号： H01L21/20
CPC分类号： H01L21/02 , H01L23/5223 , H01L27/0688 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a three-dimensional capacitor network may include forming a first horizontal MIM capacitor on a semiconductor substrate and forming a first interlayer insulating layer on the first horizontal MIM capacitor. A first vertical capacitor electrode is then formed in the first interlayer insulating layer and a second horizontal MIM capacitor is formed on the first interlayer insulating layer. This second horizontal MIM capacitor may be formed by forming an upper capacitor electrode and a lower capacitor electrode. The upper capacitor electrode may be electrically connected by the first vertical capacitor electrode to an upper capacitor electrode of the underlying first MIM capacitor. The lower capacitor electrode, which may be formed in the first interlayer insulating layer, may extend opposite the upper electrodes of the first and second MIM capacitors.
摘要翻译：形成三维电容器网络的方法可以包括在半导体衬底上形成第一水平MIM电容器，并在第一水平MIM电容器上形成第一层间绝缘层。然后在第一层间绝缘层中形成第一垂直电容器电极，并且在第一层间绝缘层上形成第二水平MIM电容器。该第二水平MIM电容器可以通过形成上电容器电极和下电容器电极而形成。上部电容器电极可以通过第一垂直电容器电极电连接到下面的第一MIM电容器的上部电容器电极。可以形成在第一层间绝缘层中的下电容器电极可以与第一和第二MIM电容器的上电极相对延伸。

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